A method of manufacturing a metal structure for an optical semiconductor device, including a treatment step (1) of immersing in and/or applying the solution containing a polyallylamine polymer a base body, the base body including an outermost layer at a portion or entire surfaces of the base body, the outermost layer including a plating of at least one selected from the group consisting of gold, silver, a gold alloy, and a silver alloy, so as to manufacture the metal structure for an optical semiconductor device having an increased adhesion to a resin material.

An electronic device includes: an insulating substrate including an obverse surface facing a thickness direction; a wiring portion formed on the substrate obverse surface and made of a conductive material; a lead frame arranged on the substrate obverse surface; a first and a second semiconductor elements electrically connected to the lead frame; and a first control unit electrically connected to the wiring portion to operate the first semiconductor element as a first upper arm and operate the second semiconductor element as a first lower arm. The lead frame includes a first pad portion to which the first semiconductor element is joined and a second pad portion to which the second semiconductor element is joined. The first and second pad portions are spaced apart from the wiring portion and arranged in a first direction with a first separation region sandwiched therebetween, where the first direction is orthogonal to the thickness direction. The first control unit is spaced apart from the lead frame as viewed in the thickness direction, while overlapping with the first separation region as viewed in a second direction orthogonal to the thickness direction and the first direction.

A power electronics module, having a DBC PCB having power semiconductors arranged thereon, and a multilayered leadframe including at least two separate subframes. No power or control routing takes place on the PCB. A region of the load source subregion is arranged between the PCB and the gate source and kelvin source subregion and is in electrical contact with the power semiconductors, and an adjoining region is located outside the PCB. A region of the drain source subregion is in electrical contact with a drain terminal on the PCB, and an adjoining region is located outside the PCB. The gate source subregion and the kelvin source subregion have a region above the load source subregion at which said subregions are in electrical contact with the power semiconductors and have an adjoining region outside the PCB which is opposite the drain source subregion and has pins bent above the PCB.

A resin enclosure includes: an inner wall portion from a wall surface defining the space to a side surface of the lead terminal close to the space; and a covering portion that covers at least a part of a top surface of a first portion of the lead terminal.

According to the present disclosure, a semiconductor apparatus comprises a housing a semiconductor chip installed in the housing, and a first radio tag installed on the housing. The first radio tag is installed in a state where rewriting from outside is not limited.

A semiconductor device of embodiments includes: a die pad; a semiconductor chip fixed on the die pad; and a sealing resin covering the semiconductor chip and at least a part of the die pad. The sealing resin has a first protruding portion provided on one side surface and a second protruding portion provided on another side surface. The cross-sectional area of the first protruding portion is equal to or more than 10% of the maximum cross-sectional area of the sealing resin. The cross-sectional area of the second protruding portion is equal to or more than 10%; of the maximum cross-sectional area. The maximum cross-sectional area is equal to or more than 6 mm.sup.2.

A semiconductor device includes a substrate, a conductive part formed on a front surface of the substrate, a semiconductor chip disposed on the front surface of the substrate, a control unit that controls the semiconductor chip, a sealing resin that covers the semiconductor chip, the control unit and the conductive part, and a first lead bonded to the conductive part and partially exposed from the sealing resin. The conductive part includes a first pad and a second pad disposed apart from each other. The first lead is bonded to the first pad and the second pad.

A package includes a first carrier including a component mounting area, a second carrier including at least one lead section, at least one electronic component mounted on the component mounting area, and an encapsulant encapsulating at least part of the at least one electronic component, encapsulating at least part of the first carrier including encapsulating the entire sidewalls of the first carrier, and encapsulating part of the second carrier, wherein the first carrier is assembled with the second carrier so that the at least one electronic component and/or the first carrier is electrically connected with the at least one lead section, and wherein the first carrier has a first thickness and the second carrier has a second thickness being smaller than the first thickness.

A semiconductor device and method is disclosed. In one example, the semiconductor device includes a first diepad including a first mounting surface and a first elevated portion elevated with respect to the first mounting surface. A first semiconductor chip is mounted on the first mounting surface. The semiconductor device further includes a second diepad including a second mounting surface. A second semiconductor chip is mounted on the second mounting surface and includes an electrical contact arranged on a top surface of the second semiconductor chip facing away from the second mounting surface. The semiconductor device further includes a first electrical connection element electrically connecting the electrical contact of the second semiconductor chip and the first elevated portion of the first diepad.

A semiconductor device includes a substrate having a first surface, a second surface, and an opening; a semiconductor device layer having a third surface and a fourth surface; a heat transfer member; source electrodes disposed on a fourth surface; and electrically conductive vias that penetrate the semiconductor device layer and a diamond layer to electrically connect the source electrodes to a metal layer. The heat transfer member includes the diamond layer and the metal layer, the diamond layer covers a bottom surface and an inner wall surface of the opening, and the metal layer is disposed on the diamond layer.