According to one embodiment, a semiconductor chip includes a first electrode, a semiconductor layer, a second electrode, a third electrode, and a metallic layer. The semiconductor layer includes a first portion, a second portion, and a third portion that is located between the first portion and the second portion. The semiconductor layer is provided on a first side of the first electrode in a first direction. The second electrode is over the first portion in the first direction. The third electrode is over the second portion in the first direction. The metallic layer is provided on a second side of the first electrode and is under the third portion in the first direction.

A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor die, a package substrate, and at least one bonding wire. The package substrate includes a dam structure to define a space where the semiconductor die is placed. The bonding wire is electrically connected between the semiconductor die and the package substrate.

A semiconductor device package and a method of manufacturing a semiconductor device package are provided. The semiconductor device package includes a carrier, a first component, a second component, and a protective element. The first component and the second component are arranged side by side in a first direction over the carrier. The protective element is disposed over a top surface of the carrier and extending from space under the first component toward a space under the second component. The protective element includes a first portion and a second portion protruded oppositely from edges of the first component by different distances, and the first portion and the second portion are arranged in a second direction angled with the first direction.

A semiconductor package includes: a base chip; semiconductor chips disposed on the base chip and including front pads disposed on a front surface opposing the base chip, rear pads disposed on a rear surface opposing the front surface, and through-vias; bumps disposed between the semiconductor chips; a dam structure disposed on at least a portion of the rear pads; and insulating adhesive layers at least partially surrounding the bumps and the dam structure, wherein the rear pads include first pads that are disposed in a center region that crosses a center of the rear surface and that are electrically connected to the through-vias, and second pads that are disposed in a peripheral region adjacent to the center region, wherein the second pads include a line pad of which at least a portion has a polygonal shape, and wherein the dam structure has a bent shape.

In one example, a semiconductor device includes a conductive structure having a conductive structure upper side. A roughening is on the conductive structure upper side and a groove is in the conductive structure extending partially into the conductive structure from the conductive structure upper side. An electronic component is attached to the conductive structure upper side with an attachment film. An encapsulant covers the electronic component, at least portions of the roughening, and at least portions of the conductive structure upper side. The groove has smoothed sidewalls that include substantially planarized portions of the roughening. The smooth sidewalls reduce flow of the attachment film across the conductive structure upper side to improve adhesion of the encapsulant to the conductive structure. Other examples and related methods are also disclosed herein.

A semiconductor package comprises a base substrate, a first semiconductor chip on the base substrate, a first dam structure which overlaps a corner of the first semiconductor chip from a plan view and is placed on the base substrate and a first fillet layer which is placed vertically between the base substrate and the first semiconductor chip, and vertically between the first dam structure and the first semiconductor chip.

A semiconductor package including a package substrate defining a cavity therein; a first semiconductor chip on the package substrate; a first bump between the package substrate and the first semiconductor chip, the first bump electrically connecting the package substrate and the first semiconductor chip; a second semiconductor chip on the package substrate, the second semiconductor chip being at least partially in the cavity; a first bonding wire electrically connecting the package substrate and the second semiconductor chip; and an underfill layer covering the first bump and at least a portion of the first bonding wire.

A semiconductor package includes a package substrate including an upper pad on an upper surface of the package substrate, a first chip structure including a plurality of first chips offset-stacked in a first direction, a controller chip on the package substrate and apart from the first chip structure in a horizontal direction, a chip connection bump between the package substrate and the controller chip, and an underfill material layer covering the chip connection bump, wherein a side surface of the underfill material layer is perpendicular to the package substrate.

A semiconductor package includes a first substrate and a first semiconductor device. The first semiconductor device is bonded to the first substrate and includes a second substrate, a plurality of first dies and a second die. The first dies are disposed between the first substrate and the second substrate. The second die is surrounded by the first dies. A cavity is formed among the first dies, the first substrate and the second substrate, and a gap is formed between the second die and the first substrate.

A base plate and power semiconductor module are provided, involving a basic body formed in one piece and having a front and rear side. The front side has a mounting area of the base plate. Along at least one of its edges, the basic body has at least one elevated integral part forming at least one sidewall projecting beyond the mounting area by a vertical height. At mounting area regions, the basic body has vertical thickness extending between the front and rear side and being larger than the vertical height of the sidewall. Along all edges, the basic body involves either at least one sidewall or at least one groove, but not both, at the same edge. Along at least one of its edges, the basic body involves one elevated integral part forming the at least one sidewall.