An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

A semiconductor element bonding substrate according to the present invention includes an insulating plate, and a metal pattern bonded to a main surface of the insulating plate. A main surface of the metal pattern on an opposite side of the insulating plate includes a bonding region to which a semiconductor element is bonded by a solder. The metal pattern includes at least one concave part located in the main surface. The at least one concave part is located closer to an edge of the bonding region in relation to a center part of the bonding region in the bonding region.

A semiconductor package includes a first semiconductor chip including a first semiconductor substrate, and a first upper pad arranged on an upper surface of the first semiconductor substrate, a first polymer layer arranged on the upper surface of the first semiconductor substrate, a second semiconductor chip mounted on the first semiconductor chip, the second semiconductor chip including a second semiconductor substrate and a second lower pad arranged under a lower surface of the second semiconductor substrate, wherein the first polymer layer has a horizontal width in a direction crossing the first polymer layer in a center region of the second semiconductor chip, as a first length, and has a horizontal width in a direction crossing two corner regions of the first polymer layer in corner regions of the second semiconductor chip, as a second length, wherein the second length is greater than the first length.

A circuit board according to an embodiment includes an insulating layer; a circuit pattern disposed on the insulating layer, and a first protective layer disposed on the insulating layer, wherein the first protective layer includes a first opening vertically overlapping at least a part of an upper surface of the circuit pattern; wherein an inner wall of the first protective layer constituting the first opening includes: a first portion having a first inclination, and a second portion disposed on the first portion and having a second inclination different from the first inclination, and wherein the first portion overlaps the circuit pattern in a horizontal direction.

A heat dissipating lid includes a first surface configured to be connected to the chip, and a groove located on the first surface. The first surface includes a first contact region. In a chip package structure, a boundary of an orthographic projection of the chip on the first surface coincides with a boundary of the first contact region. The groove is located outside the first contact region and connected to the first contact region, and the groove extends along at least a portion of the boundary of the first contact region. The heat dissipating lid is applicable to the chip package structure and configured to dissipate heat for the chip.

A semiconductor package includes a metallic substrate, the metallic substrate including a roughened surface, a semiconductor die including bond pads, and an adhesive between the roughened surface of a topside of the metallic substrate and the semiconductor die, therein bonding the semiconductor die to the metallic substrate. The adhesive includes a resin. The metallic substrate further includes a groove about a perimeter of the semiconductor die on the roughened surface, the groove having a surface roughness less than a surface roughness of the roughened surface of the metallic substrate. The groove straddles the topside and a sidewall of the metallic substrate.

An electronic chip includes a first main surface, intended to be glued to a substrate, a second main surface, and lateral surfaces. The second main surface includes a central area and a locally patterned peripheral area. The locally patterned peripheral area successively forms, from the central area, a first portion having a first thickness and a second portion having a second thickness. The first thickness is smaller than the thickness of the central area. The second thickness is greater than the first thickness and smaller than the thickness of the central area.

A semiconductor package includes a package substrate a first semiconductor chip disposed on an upper surface of the package substrate, a dam structure disposed within the pad free region on the first surface of the first semiconductor chip, a first spacer chip attached to the upper surface of the package substrate, a plurality of second semiconductor chips stacked on the first spacer chip and the first semiconductor chip using adhesive films, first bonding wires electrically connecting each of the first chip pads of the first semiconductor chip to each of first substrate pads of the package substrate, respectively, and a molding covering the first spacer chip, the first semiconductor chip, and the plurality of second semiconductor chips. The first semiconductor chip includes a pad region on which the first chip pads are disposed and a pad free region. The spacer chip is spaced apart from the first semiconductor chip along a first direction.

In order to achieve the above-described objects, according to an aspect of the present disclosure, a display device includes a substrate which includes an active area and a non-active area extending from the active area and including a pad area and is formed of any one of a transparent conducting oxide and an oxide semiconductor; a plurality of inorganic insulating layers disposed on the substrate; a dam member having one end disposed on the pad area and the other end disposed at the outside of the substrate; and a plurality of flexible films which is disposed to cover the dam member and has one end disposed in the pad area. Accordingly, the dam member which covers the pad area is formed to minimize the crack of the plurality of inorganic insulating layers at the edge of the substrate.

The present disclosure relates to a semiconductor chip that allows electrical connections to be protected and a manufacturing method therefor. A semiconductor chip has a strip-shaped region including a plurality of recesses on a side surface thereof. The recesses are arranged in a matrix of rows and columns on the side surface of the semiconductor chip or in a zig-zag pattern in the region. At least two of the strip-shaped regions are formed. The strip-shaped regions are formed in different positions between the vicinity of the center and opposed ends of the side surface. The strip-shaped region is partly inclined. The present disclosure can be applied for example to a semiconductor chip for a semiconductor device in which connections for electrically connecting the semiconductor chip and the substrate are protected with underfill.