The disclosure provides an electronic device and a manufacturing method thereof. The electronic device includes a substrate, an electronic element, an underfill layer, and a protective structure. The electronic element is disposed on the substrate. At least a portion of the underfill layer is disposed between the substrate and the electronic element. A thickness of the underfill layer is not greater than a height from a surface of the substrate to an upper surface of the electronic element. The protective structure is disposed on the substrate and adjacent to the underfill layer. The electronic device and the manufacturing method thereof of the disclosure may effectively control an area of the underfill layer.

A package structure includes a redistribution structure, a die and an underfill layer. The redistribution structure includes a first insulating layer, a second insulating layer, a first redistribution layer and a first alignment mark. The first redistribution layer and the first alignment mark are located between the first insulating layer and the second insulating layer. The die is attached to the redistribution structure. The second insulating layer includes a trench laterally located between the first alignment mark and the die. The underfill layer is located between the redistribution structure and the die. A portion of the underfill layer is filled in the trench.

Provided is a semiconductor package, the semiconductor package including: a package substrate having an upper surface on which a plurality of bonding pads are arranged; a semiconductor chip disposed on the package substrate, and having an upper surface on which a plurality of chip pads are arranged; an adhesive layer extending onto the upper surface of the package substrate between the semiconductor chip and the package substrate; a dam structure disposed around the adhesive layer, and surrounding a side surface of the adhesive layer; and external connection bumps disposed below the package substrate, and electrically connected to the plurality of bonding pads, wherein the external connection bumps are located below a region covered by the adhesive layer of the package substrate, and an area of the adhesive layer is greater than an area of a region in which the external bumps are disposed.

A semiconductor package and a method for forming the same are provided. The method includes: providing a substrate; mounting a semiconductor die on a top surface of the substrate; forming a barrier wall on a peripheral area of a top surface of the semiconductor die; dispensing a first fluid material on the top surface of the semiconductor die, wherein the barrier wall prevents the first fluid material from flowing across it; and curing the first fluid material to form a back side metallization (BSM) layer.

A method includes attaching a permeable plate to a metal lid, with the permeable plate including a metallic material, and dispensing a liquid-metal-comprising media to a first package component. The first package component is over and bonded to a second package component. The liquid-metal-comprising media includes a liquid metal therein. The method further includes attaching the metal lid to the second package component. During the attaching, the liquid-metal-comprising media migrates into the permeable plate to form a composite thermal interface material.

A semiconductor device package includes a semiconductor die including bond pads and an underfill inlet side, a substrate including a first metal layer and lower metal layers underneath the first metal layer, a plurality of metal contacts and trace segment lines disposed in the first metal layer, and a plurality of solder bump rows. Each of the solder bump rows is oriented substantially parallel to the inlet side of the semiconductor die and electrically connects bond pads of the semiconductor die with corresponding metal contacts in the first metal layer of the substrate. Each of the trace segment lines is oriented substantially parallel to the inlet side of the semiconductor die, is electrically coupled to a respective solder bump row of the plurality of solder bump rows, and includes trace segments disposed in the first metal layer and trace segments disposed in one or more of the lower metal layers.

A stacked package device has a first package and a second package vertically stacked and electrically connected to each other. One or each of the first package and the second package includes a first substrate, a second substrate and an intermediate substrate. A first flip-chip and a second flip-chip are respectively mounted on opposite surfaces of the first substrate and the second substrate. The intermediate substrate is electrically connected between the opposite surfaces of the first substrate and the second substrate for signal transmission between the first flip-chip and the second flip-chip. The use of the intermediate substrate avoids the structure damage resulting from thermal stress. Since no encapsulant is provided to cover each flip-chip, the problem of separation between the encapsulant and the substrates is avoided.

In a general aspect, a semiconductor device assembly includes a conductive member, a conductive adhesive disposed on the conductive member, and a semiconductor die disposed on the conductive adhesive. The conductive adhesive couples the semiconductor die with the conductive member. The device assembly further includes a barrier included in the conductive member. The barrier is proximate to an edge of the semiconductor die and configured to inhibit outflow of the conductive adhesive.

A semiconductor device package and a method of manufacturing a semiconductor device package are provided. The semiconductor device package includes a carrier, a first component, a second component, and a protective element. The first component and the second component are arranged side by side in a first direction over the carrier. The protective element is disposed over a top surface of the carrier and extending from space under the first component toward a space under the second component. The protective element includes a first portion and a second portion protruded oppositely from edges of the first component by different distances, and the first portion and the second portion are arranged in a second direction angled with the first direction.

A semiconductor chip is provided. The semiconductor chip may include a front side including a control chip contact and a first controlled chip contact, a back side including a second controlled chip contact, a backside metallization formed over the back side in contact with the second controlled chip contact, and a stop region extending at least partially along an outer edge of the back side between a contact portion of the backside metallization and the outer edge of the back side. The contact portion is configured to be attached to an electrically conductive structure by a die attach material, a surface of the stop region is recessed with respect to a surface of the contact portion, and/or the surface of the stop region has a lower wettability with respect to the die attach material than the contact portion.