Microelectronic deviceshaving at least one conductive contact structure adjacent a silicide regionare formed using methods that avoid unintentional contact expansion and contact reduction. A first metal nitride liner is formed in a contact opening, and an exposed surface of a polysilicon structure is thereafter treated (e.g., cleaned and dried) in preparation for formation of a silicide region. During the pretreatments (e.g., cleaning and drying), neighboring dielectric material is protected by the presence of the metal nitride liner, inhibiting expansion of the contact opening. After forming the silicide region, a second metal nitride liner is formed on the silicide region before a conductive material is formed to fill the contact opening and form a conductive contact structure (e.g., a memory cell contact structure, a peripheral contact structure).

A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the fin structure adjacent to the S/D region. The gate structure includes a gate stack disposed on the fin structure and a gate capping structure disposed on the gate stack. The gate capping structure includes a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap. The semiconductor device further includes a first contact structure disposed over the gate stack. A portion of the first contact structure is disposed within the gate capping structure and is separated from the gate stack by a portion of the conductive gate cap.

An antifuse structure including a first metal line, a top via above and directly contacting the first metal line, a second metal line, and a conductive etch stop layer separating both the first metal line and the second metal line from an underlying layer, where a first portion of the conductive etch stop layer directly beneath the first metal line comprises a first extension region and a second portion of the conductive etch stop layer directly beneath the second metal line comprises a second extension region opposite the first extension region.

A semiconductor structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes source/drain epitaxial structures formed on opposite sides of the gate structure. The structure also includes an inter-layer dielectric (ILD) structure formed over the gate structure. The structure also includes a contact blocking structure formed through the ILD structure over the source/drain epitaxial structure. A lower portion of the contact blocking structure is surrounded by an air gap, and the air gap is covered by a portion of the ILD structure.

A semiconductor structure includes a first dielectric layer on a substrate, a conductive structure disposed in the first dielectric layer and including a terminal portion and an extending portion connecting the terminal portion and extending away from the terminal portion, a second dielectric layer disposed on the first dielectric layer, a conductive via through the second dielectric layer and directly contacting the extending portion, and a dummy via through the second dielectric layer and directly contacting the terminal portion. In a cross-sectional view, a width of the dummy via is smaller than 50% of a width of the conductive via.

Representative implementations provide techniques for processing integrated circuit (IC) dies and related devices, in preparation for stacking and bonding the devices. The disclosed techniques provide removal of processing residue from the device surfaces while protecting the underlying layers. One or more sacrificial layers may be applied to a surface of the device during processing to protect the underlying layers. Processing residue is attached to the sacrificial layers instead of the device, and can be removed with the sacrificial layers.

A semiconductor structure includes a semiconductor substrate, a dielectric layer, a tungsten plug, a conductive plug, and a contact barrier. The dielectric layer is over a semiconductor substrate. The tungsten plug is in the dielectric layer. The conductive plug is on the tungsten plug. The contact barrier includes a sidewall barrier on a sidewall of the conductive plug and a bottom barrier between the conductive plug and the tungsten plug. A thickness of the sidewall barrier is greater than a thickness of the bottom barrier.

A semiconductor device includes a substrate, a plurality of metal lines on the substrate, a protuberance layer formed on upper portions of sidewalls of the metal lines, anda liner layer formed between the metal lines and between the protuberance layer. The liner layer connects the protuberance layer, and an airgap exists in the liner layer below a bottom surface of the protuberance layers.

A method of processing a substrate includes providing a substrate with a line pattern including lines extending in a longitudinal direction and exposing the line pattern to a directional beam. The directional beam has an azimuthal component substantially parallel to the longitudinal direction. Exposing the line pattern to the directional beam may concurrently deposit material on sidewall surfaces of the line pattern and etch surfaces of the line pattern with a normal component parallel to the longitudinal direction. The line pattern may have localized defects. The deposited material may mitigate pinch defects in the line pattern. The etched surfaces may mitigate bridge defects in the line pattern. A controller may be configured to cause the substrate to be processed according to the method. The controller may be included in a system further including a beam source and a substrate positioner.

A method for filling a gap in a semiconductor structure includes: forming the gap between two raised portions of the semiconductor structure, the gap having a bottom surface and two lateral surfaces each extending upwardly from the bottom surface along one of the raised portions to terminate at an upper surface of a corresponding one of the raised portions; and forming a filler element in the gap in a bottom-up manner that avoids the filler element being formed laterally.