Some example embodiments are directed to a semiconductor device including a substrate including a chip region and a peripheral region, a circuit wiring layer on the chip region of the substrate, an interlayer insulating layer on the chip region of the substrate covering the circuit wiring layer, and extending on the peripheral region of the substrate, a chip pad on the interlayer insulating layer on the chip region, and connected to the circuit wiring layer, and a test pad on the interlayer insulating layer on the peripheral region. A thickness of the test pad is less than a thickness of the chip pad in a direction vertical to an upper surface of the substrate.

A test structure includes at least one test element. The test element includes a substrate, an isolation structure, and multiple word lines. The isolation structure is located in the substrate. The isolation structure defines multiple active regions in the substrate. The word lines include multiple first word lines and multiple second word lines that are alternately arranged. The first word lines are located in the active regions. The second word lines are not located in the active regions and are located on the isolation structure. The first word lines and the second word lines are insulated from the substrate.

A testing structure for a semiconductor wafer substrate is formed from a trench and a via connected to the perimeter of the trench. The via also connects to an interconnection. The via is filled with a first electrically conductive material, and the trench also includes a second electrically conductive material that is more stable than the first electrically conductive material. A conductive path extending vertically from the interconnection to an upper surface of the testing structure passes through only the first electrically conductive material. The use of the second electrically conductive material reduces or prevents migration of atoms/ions within the first electrically conductive material and so increases system reliability.

A semiconductor device includes a semiconductor die, a detection structure, a path control circuit and a detection circuit. The semiconductor die includes a central region in which a semiconductor integrated circuit is provided and an external region surrounding the central region. The detection structure is provided in the external region. The path control circuit includes a plurality of switches that controls electrical connection of the detection structure. The detection circuit determines whether a defect is present in the semiconductor die and a location of the defect based on a difference signal. The difference signal corresponds to a difference between a forward direction test output signal and a backward direction test output signal obtained by propagating a test input signal through the detection structure in a forward direction and a backward direction, respectively, via the path control circuit.

A semiconductor package, includes: a base chip having a front surface and a back surface opposite to the front surface, the base chip including bump pads, wafer test pads, and package test pads, disposed on the front surface; connection structures disposed on the front surface of the base chip and connected to the bump pads; and semiconductor chips stacked on the back surface of the base chip, wherein each of the wafer test pads is smaller than the package test pads.

A standby current detection circuit includes multiple first transistors. The first transistors are coupled in series to form a first detection circuit string, where N is a positive integer. The first detection circuit string is disposed on a scribe lane of a wafer, and the first detection circuit string is operated in a standby state and serves as a test medium for a standby current.

An electronic product includes a number of die and an interposer. The die are coupled to the interposer. Each respective die includes an edge integrity detection structure extending along at least part of an edge of the respective die. The interposer includes at least one pad coupled to at least one edge integrity detection structure of the die.

A test structure including the following members is provided. A substrate includes an array region and a peripheral region. The array region has a first side and a second side opposite to each other. An isolation structure is located in the substrate. The isolation structure defines active regions in the substrate of the array region. Word lines pass through the active regions and are insulated from the substrate. The word lines include first word lines and second word lines arranged alternately. First contacts are electrically connected to the first word lines. Second contacts are electrically connected to the second word lines. The first contacts and the second contacts are arranged in a staggered manner. First conductive lines are electrically connected to the first contacts. Second conductive lines are electrically connected to the second contacts. The second conductive lines are extended from the peripheral region into the array region.

A scribe line structure is provided. The scribe line structure includes a die region, a scribe line region, and one or more circuit probing pads. The die region is disposed on a semiconductor wafer. The scribe line region surrounds the die region. The one or more circuit probing pads are disposed on a first top surface of the die region and a second top surface of the scribe line region.

An electronic product includes a package substrate, a number of die, and an interposer. The die are coupled to the interposer, and each respective includes an edge integrity detection structure extending along at least part of an edge of the respective die. The package substrate includes at least one pad coupled to at least one edge integrity detection structure of at least one die of the die.