Methods and pad structures to test via accuracy are provided. A method according to the present disclosure includes forming a first pad and a second pad on a device component, wherein the second pad includes a via landing area and a clearance opening, providing a core substrate that includes a cavity, placing the device component in the cavity, forming a build-up film over the device component and the core substrate, forming a first contact via extending through the build-up film to contact the landing area and a second contact via extending through build-up film and the clearance opening, and performing a continuity test to determine whether the second contact via is in contact with the second pad.

Improved breakdown test structures are provided. In some embodiments, multiple test structures may be combined into a single (e.g., two-terminal) test structure for monitoring interconnect voltage breakdown (VBD) of representative interconnect structures within scribe line regions.

Disclosed herein are an integrated circuit die assembly and a method for forming the integrated circuit die assembly. The integrated circuit die assembly includes an integrated circuit (IC) die stack comprising a top IC die and a bottom IC die. The top IC die includes a first layout of shared contact pads that are arranged identically to a second layout of shared contact pads disposed on the bottom IC die, the shared contact pads being configured for both contacting with a testing probe and bumping. The integrated circuit die further includes a package substrate coupled with the bottom IC die. The shared contact pads of the top IC die include probing marks, and the shared contact pads of the bottom IC die are coupled with solder bumps.

A chip mounted substrate may include: a film-type substrate including: a first edge region and a second edge region opposing in a first direction; and a third edge region and a fourth edge region connecting the first edge region and the second edge region and opposing in a second direction intersecting the first direction; and a semiconductor chip on the film-type substrate. The film-type substrate may include: an insulating film; chip bonding pads electrically connected to the semiconductor chip; external connection pads electrically connected to the chip bonding pads; and test pads electrically connected to the chip bonding pads and the external connection pads. The test pads may be in at least three of the first edge region, the second edge region, the third edge region, and the fourth edge region.

Semiconductor dies and semiconductor wafers are provided. A first semiconductor die, a second semiconductor die, and a detector are configured to determine the degree of alignment accuracy with the first semiconductor die being coupled to the second semiconductor die. First test pads of each of first test pad groups of the first semiconductor die are electrically connected to each other through a line extending in a first direction, and second test pads of each of second test pad groups of the second semiconductor die are electrically connected to each other through a line extending in a third direction transversing the first direction. The detector detects misalignment between the first semiconductor die and the second semiconductor die, based on current flowing between the first test pads of each first test pad group and the second test pads of each second test pad group.

Integrated circuit (IC) devices having gate vias adjacent metal contacts over source and drain bodies in transistors.

An IC device may include a test structure having a pair of electrodes, a floating electrode and a gate electrode in a dummy transistor, both the floating and gate electrodes adjacent a metal line grounded by the dummy transistor. Voltage contrast analysis (e.g., with e-beam scanning) of a gate via on the floating electrode may be used to detect a via short to the metal line. The test structure may include vast arrays of the electrode pairs.

A stacked semiconductor apparatus, which is formed by stacking a first die and a second die, includes the first die including a first test module configured to generate a test pattern and a plurality of transmission multiplexers, each of which one input receives the test pattern, the second die including a plurality of reception multiplexers and a second test module configured to control the plurality of reception multiplexers, and a connection part including a plurality of signal transmission members electrically connected to outputs of the plurality of transmission multiplexers and each connected to one input of the reception multiplexers, and a robust transmission member configured to transmit a signal between the first test module and the second test module, wherein the second test module transmits a signal, which is received by the reception multiplexer through the signal transmission member, to the first test module through the robust transmission member, and the first test module detects a fault of the signal transmission member by comparing the test pattern with the signal transmitted by the second test module through the robust transmission member.

A semiconductor device includes: a first standard cell and a second standard cell at different positions in at least one of a first direction and a second direction parallel to an upper surface of a semiconductor substrate, the first standard cell and the second standard cell intersecting each other; a signal interconnection connecting the first standard cell and the second standard cell; and a monitoring interconnection connected to the signal interconnection in a vertical direction perpendicular to the upper surface and at a first level higher than a second level of the signal interconnection in the vertical direction, wherein the monitoring interconnection includes a monitoring pad in an uppermost interconnection layer at an uppermost level in the vertical direction.

A semiconductor device may include a first substrate including device and edge regions, a first insulating structure on the first substrate, first metal pads and first dummy pads at the uppermost end of the first insulating structure, a second insulating structure on the first insulating structure, second metal pads and second dummy pads at the lowermost end of the second insulating structure, a first interconnection structure in the first insulating structure, electrically connected to the first metal pads and electrically isolated from the first dummy pads, and a second interconnection structure in the second insulating structure, electrically connected to the second metal pads, and electrically isolated from the second dummy pads. Ones of the first metal pads may be in contact with respective ones of the second metal pads on the device region, and ones of the first dummy pads may be in contact with respective ones of the second dummy pads on the edge region.

A contaminant detection device includes: a contact module configured to contact a wafer; a detection module on the contact module, the detector being configured to change color by reacting with a metal ion; and a sensing module configured to sense a color change of the detection module.