The present disclosure provides a semiconductor structure, including a substrate, a gate structure over the substrate, including a work function layer over the substrate, a dielectric layer at least partially surrounding the gate structure, and a capping layer over the gate structure, wherein a bottom of the capping layer includes at least one protrusion protruding toward the substrate.

A method of curing or otherwise processing semiconductor wafers in an environmentally controlled process chamber includes: loading a plurality of semiconductor wafers into the process chamber such that pairs of adjacent semiconductor wafers are spaced apart from one another by gaps therebetween; introducing a process gas into the process chamber containing the plurality of semiconductor wafers; and drawing gas from the process chamber through one or more exhaust manifolds. Suitably, each exhaust manifold includes a plurality of inlet orifices through which gas is drawn into the exhaust manifold, at least one of the inlet orifices facing and aligning with each of the gaps.

A method for fabricating a semiconductor device includes exposing one or more surfaces of a conduction channel of a transistor; overlaying the one or more surfaces with a dielectric interfacial layer; overlaying the dielectric interfacial layer with a blocking layer; performing a first annealing process to densify the dielectric interfacial layer; overlaying the blocking layer with a first high-k dielectric layer; forming one or more threshold voltage modulation layers over the first high-k dielectric layer; performing a second annealing process to adjust a doping profile of the first high-k dielectric layer; and overlaying the first high-k dielectric layer with a second high-k dielectric layer.

A method according to the present disclosure includes receiving a structure that includes a source/drain feature sandwiched between a first channel region and a second channel region, a first dummy gate stack over the first channel region, a first gate spacer extending along a sidewall of the first dummy gate stack, a second dummy gate stack over the second channel region, a second gate spacer extending along a sidewall of the second dummy gate stack, and an interlayer dielectric (ILD) layer over the source/drain feature and disposed between the first gate spacer and the second gate spacer, selectively recessing the ILD layer to form a top recess, after the selectively recessing, performing an ion implantation process to the structure, and after the ion implantation process, forming a capping layer in the top recess.

A Plasma Enhanced Anneal (PEA) includes a exposing a top surface region of a substrate to a plasma to reduce the required activation energy temperature to anneal dopants for microelectronic devices. The plasma in a PEA process bombards surfaces with ions and atoms created in the plasma which allows controllable kinetic energy and ion flux to be transferred to the top surface region of the substrate and activate dopants at temperatures as low as 300 C. The plasma energy of the ions is known to dissipate into a region only a few nanometers in depth with energy densities large enough to activate dopants. PEA processing may be a promising method for dopant activation at temperatures lower than thermal techniques alone. PEA processing may also result in reduced thermal budget necessary for form silicides, anneal silicides, and anneal high-k dielectric materials.

Disclosed are a laser annealing system and a method of fabricating a semiconductor device using the same. The laser annealing system having multiple laser devices may include a stage, on which a substrate is loaded, a light source generating a plurality of laser beams to be provided to the substrate, an optical delivery system disposed between the light source and the stage and used to deliver the laser beams, a homogenizing system disposed between the optical delivery system and the stage, the homogenizing system including an array lens including a plurality of lens cells which allow the laser beams to pass therethrough and homogenize the laser beams, and an imaging optical system disposed between the homogenizing system and the stage to image the laser beams on the substrate.

A processing apparatus configured to process a processing target object includes a modifying device configured to radiate laser light to an inside of the processing target object to form multiple modification layers along a plane direction; and a controller configured to control an operation of the modifying device at least. The controller controls the modifying device to form, in the forming of the modification layers, a first modification layer formation region in which cracks that develop from neighboring modification layers along the plane direction are not connected, and also controls the modifying device to form, in the forming of the modification layers, a second modification layer formation region in which cracks that develop from neighboring modification layers along the plane direction are connected.

A heat treatment apparatus is a heat treatment apparatus managing a dummy wafer. The heat treatment apparatus includes: a heat treatment part performing a heat treatment on the dummy wafer; a damage detection part detecting a damage of the dummy wafer; and a controller determining whether or not the dummy wafer can be used based on damage information detected by the damage detection part.

A substrate, a first layer disposed on the substrate, and a second layer disposed on the first layer are provided. An opening is etched through the second layer to the first layer. A first portion of the first layer is etched through the opening using a first etchant, to expose a surface of the substrate through the opening. A feature is deposited on the surface of the substrate through the opening. A second portion of the first layer is etched using a gaseous etchant, to release the substrate from the second layer.

A method for manufacturing a multilayer structure by direct bonding between a first substrate and a second substrate, the method including the steps of: providing a first substrate and a second substrate respectively including a first bonding surface and a second bonding surface, contacting the first bonding surface and the second bonding surface so as to create a direct bonding interface between the first substrate and the second substrate, placing at least the direct bonding interface in a cationic aqueous solution including deionized water and cationic species originating from at least one element of the first and/or of the second column of the periodic table of elements, and applying a heat treatment at a temperature comprised between 20 C. and 350 C. so as to obtain the multilayer structure.