The present disclosure provides a semiconductor structure, including a substrate, a gate structure over the substrate, including a work function layer over the substrate, a dielectric layer at least partially surrounding the gate structure, and a capping layer over the gate structure, wherein a bottom of the capping layer includes at least one protrusion protruding toward the substrate.

A method according to the present disclosure includes receiving a structure that includes a source/drain feature sandwiched between a first channel region and a second channel region, a first dummy gate stack over the first channel region, a first gate spacer extending along a sidewall of the first dummy gate stack, a second dummy gate stack over the second channel region, a second gate spacer extending along a sidewall of the second dummy gate stack, and an interlayer dielectric (ILD) layer over the source/drain feature and disposed between the first gate spacer and the second gate spacer, selectively recessing the ILD layer to form a top recess, after the selectively recessing, performing an ion implantation process to the structure, and after the ion implantation process, forming a capping layer in the top recess.

A semiconductor device structure and a formation method are provided. The method includes forming a sacrificial base layer over a substrate and forming a semiconductor stack over the sacrificial base layer. The semiconductor stack has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes forming a gate stack to partially cover the sacrificial base layer, the semiconductor layers, and the sacrificial layers. The method further includes removing the sacrificial base layer to form a recess between the substrate and the semiconductor stack. In addition, the method includes forming a metal-containing dielectric structure to partially or completely fill the recess. The metal-containing dielectric structure has multiple sub-layers.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a gate structure on the substrate; a plurality of inner spacer layers on sidewalls of the gate structure; a plurality of outer spacer layers on the plurality of inner spacer layers; a plurality of air gaps between the inner spacer layers and the outer spacer layers; a bottom dielectric layer on the substrate and laterally surrounding the outer spacer layers; a bottom capping layer on the bottom dielectric layer, the inner spacer layers, the air gaps, the outer spacer layers, and the gate structure; a conductive layer on the bottom capping layer and including a plurality of conductive wires; a top capping layer positioned on the conductive layer; and a plurality of air spacers positioned between the conductive wires.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a gate structure on the substrate; a plurality of inner spacer layers on sidewalls of the gate structure; a plurality of outer spacer layers on the plurality of inner spacer layers; a plurality of air gaps between the inner spacer layers and the outer spacer layers; a bottom dielectric layer on the substrate and laterally surrounding the outer spacer layers; a bottom capping layer on the bottom dielectric layer, the inner spacer layers, the air gaps, the outer spacer layers, and the gate structure; a conductive layer on the bottom capping layer and including a plurality of conductive wires; a top capping layer positioned on the conductive layer; and a plurality of air spacers positioned between the conductive wires.

A semiconductor memory device may include a substrate including a cell region and a peripheral region defined around the cell region, and a gate structure which may include sequentially stacked first, second, and third conductive layers including different materials, the first conductive layer including polysilicon. A capping layer may be on the third conductive layer, and a spacer may be on a sidewall of each of the first to third conductive layers and the capping layer. A first contact may extend through the capping layer and into the third conductive layer, with the first contact in contact with the second conductive layer, and separated from the first conductive layer. The first contact may include a first portion in the third conductive layer and a second portion in the capping layer. A width of the first portion may be greater than a width of the second portion in a horizontal direction.

A method for manufacturing a semiconductor structure includes: forming a gate electrode; forming a gate dielectric; forming a channel unit on the gate dielectric opposite to the gate electrode, the channel unit including: a lower channel layer including a first composition that is uniform throughout the lower channel layer, the lower channel layer having a first band gap; and an upper channel layer including a second composition that is different from the first composition and that is uniform throughout the upper channel layer, the upper channel layer having a second band gap greater than the first band gap; and forming a source electrode and a drain electrode that are electrically connected to the lower channel layer, and that are spaced apart from each other.

A method for fabricating a semiconductor device including a self-aligned top via includes subtractively etching a conductive layer to form at least a first conductive line on a substrate. After the subtractive etching, the method further includes forming a barrier layer along the substate and along the first conductive line, planarizing at least portions of the barrier layer to obtain at least an exposed first conductive line, recessing at least the exposed first conductive line to form a first recessed conductive line, and forming conductive material in a via opening on the first recessed conductive line.