The present disclosure provides a semiconductor structure, including a substrate, a gate structure over the substrate, including a work function layer over the substrate, a dielectric layer at least partially surrounding the gate structure, and a capping layer over the gate structure, wherein a bottom of the capping layer includes at least one protrusion protruding toward the substrate.

According to one or more embodiments, a method includes positioning a substrate within a processing chamber. The substrate includes a hardmask layer disposed over a surface of the substrate, a first layer disposed over the hardmask layer, and a second layer disposed over the first layer. The method further includes flowing a process gas into the processing chamber, and delivering a microwave energy for a period of time to the process gas to selectively etch the hardmask layer and the first layer, wherein delivering the microwave energy to the process gas does not generate a plasma.

Embodiments discloses a semiconductor structure and a fabricating method. The method includes: forming a contact hole on a substrate; forming a first doped layer on a surface of the contact hole, and annealing the first doped layer; forming at least one second doped layer on the first doped layer, and annealing each of the at least one second doped layer; and forming a third doped layer on the at least one second doped layer to fill up the contact hole. A thickness of the at least one second doped layer is greater than a thickness of the third doped layer, and the thickness of the third doped layer is greater than the thickness of the first doped layer. Annealing not only can repair lattice mismatch and lattice defect in the first doped layer/second doped layer, but also can improve surface roughness of the first doped layer/second doped layer.

Semiconductor structures and methods of forming the same are provided. In one embodiment, a semiconductor structure includes an active region over a substrate, a gate structure disposed over the active region, and a gate contact that includes a lower portion disposed over the gate structure and an upper portion disposed over the lower portion.

A semiconductor device includes active regions extending in a first direction on a substrate; a gate electrode intersecting the active regions on the substrate, extending in a second direction, and including a contact region protruding upwardly; and an interconnection line on the gate electrode and connected to the contact region, wherein the contact region includes a lower region having a first width in the second direction and an upper region located on the lower region and having a second width smaller than the first width in the second direction, and wherein at least one side surface of the contact region in the second direction has a point at which an inclination or a curvature is changed between the lower region and the upper region.

An etching technique removes a film by supplying a first gas containing a first halogen element and a second gas containing a second halogen element. In embodiments, the first gas includes a Group 13 halide and the second gas includes a chlorine-containing compound with a Group 16 element. The gases are introduced with different start times, optionally with a period of simultaneous supply, so the first gas weakens bonds in a nitride or oxide and the second gas accelerates removal. The method suits cleaning deposits from internal surfaces of a process vessel and etching films on a substrate. After etching, a cyclic purge removes residual species. A pre-coating step may form a nitride film to suppress diffusion of elements and stabilize initial film growth.

A method for wafer treatment is disclosed. A wafer is provided with a main surface, a surface layer, and a base layer. The surface layer is disposed between the main surface and the base layer, and the surface layer covers the base layer and exposes the main surface. Then, at least one laser process is performed to fully irradiate the main surface and the surface layer with a first laser to generate a plurality of optimized regions in the main surface and the surface layer, so that the optimized regions form at least one stress-relieving array.

According to one embodiment, a semiconductor device includes a semiconductor layer including a source area, a drain area and a channel area, a first insulating layer, an etching stopper layer located immediately above the channel area and being thinner than the first insulating layer, a second insulating layer provided on the etching stopper layer and being thicker than the first insulating layer, a gate electrode, a third insulating layer which covers the etching stopper layer, the second insulating layer and the gate electrode and covers the first insulating layer immediately above the source area and immediately above the drain area, a source electrode in contact with the source area, and a drain electrode in contact with the drain area.

Disclosed are a semiconductor photoresist composition and a method of forming patterns using the semiconductor photoresist composition. The semiconductor photoresist composition includes an organometallic compound represented by Chemical Formula 1 and a solvent and a method of forming patterns using the same.

A planarization method includes the following steps. A silicon layer is deposited on a substrate, and a top surface of the silicon layer includes a lower portion and a bump portion protruding upwards from the lower portion. An ion bombardment etching process is performed to the silicon layer for reducing a surface step height of the silicon layer. The top surface of the silicon layer is etched by the ion bombardment etching process to become a post-etching top surface, and a distance between a topmost portion of the post-etching top surface and a bottommost portion of the post-etching top surface in a vertical direction is less than a distance between a topmost portion of the bump portion and the lower portion in the vertical direction before the ion bombardment etching process. Subsequently, a chemical mechanical polishing process is performed to the post-etching top surface of the silicon layer.