A semiconductor device package is provided. The semiconductor device package includes a stack structure comprising a plurality of electronic components vertically stacked relative to each other. Each of the plurality of electronic components is configured to provide electrical connectivity in a vertical direction. A first thermal element surrounds lateral surfaces of the stack structure and is thermally coupled to a lateral surface of at least one of the electronic components, thereby enhancing lateral heat dissipation efficiency of the stack structure.

A semiconductor package includes: a package substrate, a first stack structure disposed on the package substrate, the first stack structure including first semiconductor chips stacked and connected to each other by bonding wires, a second stack structure disposed on the first stack structure, and including second semiconductor chips stacked, the second stack structure having an overhang region protruding beyond an uppermost first semiconductor chip of the first stack structure among the first semiconductor chips, an adhesive member covering a lower surface of the second stack structure and adhered to a portion of upper surfaces of the first stack structure, and an encapsulant disposed on the package substrate and covering the first stack structure and the second stack structure, wherein at least a portion of the bonding wires are buried in the die adhesive film in the overhang region to support the second stack structure.

A semiconductor memory device includes a first memory die, a second memory die disposed above the first memory die via adhesives, a first wiring connected to the first memory die, and configured to apply a power supply voltage to the first memory die, a first switch element connected to the first wiring, a second wiring connected to the second memory die, and configured to apply the power supply voltage to the second memory die, a second switch element connected to the second wiring, and a third wiring configured to electrically connect to the first wiring via the first switch element, and configured to electrically connect to the second wiring via the second switch element. The first switch element and the second switch element are independently controllable.

A semiconductor device assembly is provided. The assembly includes an outer semiconductor device which has an active surface and a back surface. The back surface includes a cut that extends to a depth between the active surface and the back surface, and uncut regions on opposing sides of the cut. The assembly further includes an inner semiconductor device disposed within the cut of the outer semiconductor device.

A semiconductor package, includes: a first semiconductor chip including first connection pads on the first front surface, and through electrodes extending perpendicularly to the first rear surface and electrically connected to at least a portion of the first connection pads; a second semiconductor chip including second connection pads on the second front surface, and on the first rear surface so that the second rear surface faces the first semiconductor chip; a dielectric layer on the second semiconductor chip; first conductive structures in the dielectric layer, and connecting the through electrodes of a first group and the second connection pads; second conductive structures in the dielectric layer, and having first and second ends, the first ends connected to the through electrodes of a second group and at least a portion of the second ends thereof being exposed from the dielectric layer; at least one third semiconductor chip including third connection pads on the third front surface, and on the dielectric layer so that the third rear surface faces the second semiconductor chip; conductive wires connecting the second conductive structures and the third connection pads.

A semiconductor device includes a memory cell structure in a cell array region, an electrode stacking structure including a plurality of electrodes and a plurality of interlayer insulation layers alternately stacked in a connection region, and a plurality of electrode contact portions penetrating at least a partial portion of the electrode stacking structure and are electrically connected to the plurality of electrodes. The plurality of electrode contact portions include first and second contact portions. The first contact portion includes a first conductive portion, and a first side insulation layer between the electrode stacking structure and the first conductive portion. The second contact portion includes a second conductive portion, and a second side insulation layer between the electrode stacking structure and the second conductive portion. The second side insulation layer has a shape or a structure different from a shape or a structure of the first side insulation layer.

In some embodiments, a semiconductor package includes a package substrate that includes a first surface, a second surface that is opposite to the first surface, first substrate pads disposed on the first surface in a first row, and second substrate pads disposed on the first surface in a second row. The semiconductor package further includes a first semiconductor chip that includes first chip pads, lower bonding wires configured to respectively couple the first chip pads and the first substrate pads, a second semiconductor chip that includes second chip pads, upper bonding wires configured to respectively couple the second chip pads and the second substrate pads, and an encapsulant disposed on the package substrate and covering the first semiconductor chip and the second semiconductor chip. The lower bonding wires are ball-bonded to the first chip pads and stich-bonded to the first substrate pads.

A semiconductor package includes a package substrate including first and second power P-pads and first and second signal P-pads, a lower layer chip including first and second power L-pads and first and second signal L-pads, an upper layer chip offset from the lower layer chip and including first and second power U-pads and first and second signal U-pads. The first power and signal P-pads are alternatingly stacked, the first power and signal L-pads are alternatingly stacked, and the first power and signal U-pads are alternatingly stacked. The second power and signal P-pads are alternatingly stacked, the second power and signal L-pads are alternatingly stacked, and the second power and signal U-pads are alternatingly stacked. Bonding wires connect the first and second power U-pads, the first and second power L-pads, the second power U-pads and P-pads, and the second signal U-pads and P-pads.

A semiconductor package includes a substrate including first bonding pads. At least one chip stack is on the substrate and includes a plurality of semiconductor chips stacked thereon. The semiconductor chips include first connection pads electrically connected to the first bonding pads, bonding wires electrically connecting the substrate to the chip stack, and connection bumps below the substrate. The semiconductor chips include a second group of semiconductor chips stacked on a first group of semiconductor chips. An uppermost semiconductor chip in the first group of semiconductor chips or a lowermost semiconductor chip in the second group of semiconductor chips further includes second connection pads electrically connected to the first connection pads, respectively. The bonding wires include first bonding wires electrically connecting the first connection pads of the semiconductor chips to each other, and second bonding wires electrically connecting the second connection pads and the first bonding pads to each other.

A semiconductor package comprises a package substrate, a first semiconductor chip comprising a semiconductor substrate, a wiring structure on the semiconductor substrate, a connection pad at an uppermost part of the wiring structure, and a protective layer on a side surface of the connection pad, a crack reduction layer on the connection pad and the protective layer and a mold layer on the crack reduction layer, wherein a coefficient of thermal expansion of the crack reduction layer is lower than a coefficient of thermal expansion of the semiconductor substrate.