A semiconductor structure includes a first back-end-of-line region coupled to a first side of a front-end-of-line region, a second back-end-of-line region coupled to a second side of the front-end-of-line region, and a thermally conducting region at least partially surrounding a perimeter of the front-end-of-line region, the first back-end-of-line region and the second back-end-of-line region.

An electronic device includes a dielectric layer including crystal grains having aligned crystal orientations the dielectric layer may be between a substrate and a gate electrode. The dielectric layer may be between isolated first and second electrodes. A method of manufacturing an electronic device may include preparing a substrate having a channel layer, forming the dielectric layer on the channel layer, and forming a gate electrode on the dielectric layer.

A semiconductor package may include a first semiconductor die having a first width; a second semiconductor die on the first semiconductor die, the second semiconductor die having a second width that is smaller than the first width; and a mold layer at least partially covering a side surface of the second semiconductor die, and a top surface of the first semiconductor die, wherein the first semiconductor die comprises at least one first detection pattern, the at least one first detection pattern being on the top surface of the first semiconductor die and in contact with a bottom surface of the mold layer.

A package for encapsulating a functional area against an environment includes a base substrate and a cover substrate, the base substrate together with the cover substrate defining at least part of the package or defining the package, and furthermore including the at least one functional area provided in the package, and a blocking way for reducing permeation between the environment and the functional area. The package may include at least one laser bonding line, and the substrates of the package can be hermetically joined to one another by the at least one laser bonding line, and the laser bonding line has a height (HL) perpendicular to its bonding plane.

A package for encapsulating a functional area against an environment includes a base substrate and a cover substrate, the base substrate together with the cover substrate defining at least part of the package or defining the package, and furthermore including the at least one functional area provided in the package, and a blocking way for reducing permeation between the environment and the functional area. The package may include at least one laser bonding line, and the substrates of the package can be hermetically joined to one another by the at least one laser bonding line, and the laser bonding line has a height (HL) perpendicular to its bonding plane.

Methods of manufacturing a sealed electrical device for embedded integrated circuit (IC) chips are described, as well as the resulting devices themselves. The sealed electrical device is created by removing material from a substrate to form a pocket in the substrate. An unencapsulated, or bare, IC chip can be placed within the pocket with connection pads of the IC chip facing outward. A gap between the IC chip and a side of the pocket can be filled with a filler. An uncured polymer can be cast over the substrate, which can be allowed to cure into a flat polymer sheet. Conductive traces can be patterned on the polymer sheet and to the connection pads of the IC chip. The conductive traces can then be coated with polymer to form a ribbon cable. Substrate can then be removed from underneath the ribbon cable, leaving substrate around the pocket to protect the IC chip.

Methods of manufacturing a sealed electrical device for embedded integrated circuit (IC) chips are described, as well as the resulting devices themselves. The sealed electrical device is created by removing material from a substrate to form a pocket in the substrate. An unencapsulated, or bare, IC chip can be placed within the pocket with connection pads of the IC chip facing outward. A gap between the IC chip and a side of the pocket can be filled with a filler. An uncured polymer can be cast over the substrate, which can be allowed to cure into a flat polymer sheet. Conductive traces can be patterned on the polymer sheet and to the connection pads of the IC chip. The conductive traces can then be coated with polymer to form a ribbon cable. Substrate can then be removed from underneath the ribbon cable, leaving substrate around the pocket to protect the IC chip.

An electronic device is provided. An example electronic device includes: a semiconductor body of Silicon Carbide, having a surface having a first portion of the surface that defines an active region of the electronic device and a second portion of the surface that is external to the active region; a metallization extending on the first portion of the surface of the semiconductor body; a passivation layer extending on part of the metallization; and an adhesion layer, based on one or more carbon allotropes, extending on the passivation layer.

Semiconductor devices and fabrication methods thereof are described. For example, a semiconductor device includes a GaN heterojunction structure disposed on a substrate. The GaN heterojunction structure includes a barrier layer disposed on a GaN layer. The semiconductor device further includes a source contact, a drain contact, and a gate electrode. The gate electrode is disposed above the GaN heterojunction structure and between the source contact and the drain contact. The semiconductor device still further includes a plurality of segments of dielectric material disposed on the barrier layer between the source contact and the drain contact.

Various embodiments of the present technology may provide a method for fabricating a semiconductor structure. The method may include receiving a source substrate having a dielectric layer and a conductive feature, selectively depositing a barrier layer only on a top surface of the conductive feature, modifying a top surface of the dielectric layer, and removing the barrier layer after modifying the dielectric layer. The method may also include cleaning a top layer of the dielectric and conductive feature prior to depositing the barrier layer.