A method for manufacturing a semiconductor device, the method including forming a fin type pattern including a lower pattern and an upper pattern on a substrate, the upper pattern including a plurality of sacrificial layers and a plurality of sheet patterns alternately stacked on the lower pattern; forming a field insulating film on the substrate and the fin type pattern such that the field insulation film covers side walls of the lower pattern; forming a passivation film on the field insulating film such that the passivation film extends along an upper surface of the field insulating film; and removing the plurality of sacrificial layers after forming the passivation film.

A high electron mobility transistor (HEMT) and method for forming the same are disclosed. The high electron mobility transistor has a GaN epi-layer, a source ohmic contact, a drain ohmic contact, a gate structure, a first metal electrode contact and a first passivation layer. The source ohmic contact and the drain ohmic contact are disposed on the epi-layer. The gate structure is disposed on the epi-layer and between the source ohmic contact and the drain ohmic contact. The first metal electrode contact is disposed above the gate structure. The first passivation layer is sandwiched between the first metal electrode contact and the gate structure.

Provided is a semiconductor chip including a semiconductor chip including a semiconductor substrate including a first surface and a second surface opposite to the first surface, a wiring layer arranged on the first surface of the semiconductor substrate, a plurality of through electrodes extending from the first surface of the semiconductor substrate to the second surface of the semiconductor substrate, a plurality of chip pads arranged on the second surface of the semiconductor substrate and electrically connected to the plurality of through electrodes, and a passivation layer arranged on the second surface of the semiconductor substrate and in contact with side surfaces of the plurality of chip pads. The passivation layer includes an insulating layer and an oxide layer arranged on the insulating layer. The insulating layer includes an insulating pattern having a first width along a horizontal direction. The oxide layer includes a first oxide pattern having a second width along the horizontal direction. The first width is greater than the second width.

A method of manufacturing the package structure includes providing a carrier on which first dies and second dies are respectively bonded to form stacks and an encapsulant laterally encapsulating the stacks, forming a dielectric layer over the stacks, forming openings in the dielectric layer to expose a portion of the second dies, forming trenches in the gaps through the encapsulant to expose the carrier, forming a cover layer on sidewalls of the trenches and sidewalls of the openings, and conformally forming a seed layer on the trenches, the openings, the carrier, the cover layer, the encapsulant, and the dielectric layer, forming a mask layer to cover a portion of the seed layer and expose the seed layer in the openings, and performing a plating process to form a conductive portion in the openings using the seed layer.

In an embodiment, a Group III nitride-based transistor device includes a source electrode, a drain electrode and a gate electrode positioned on a first major surface of a Group III nitride based-based layer, wherein the gate electrode is laterally arranged between the source electrode and the drain electrode, a passivation layer arranged on the first major surface and a field plate coupled to the source electrode, the field plate having a lower surface arranged on the passivation layer. The field plate is laterally arranged between and laterally spaced apart from the gate electrode and the drain electrode.

This insulation module is provided with: a first conductor and a second conductor, which are buried in an insulating layer so as to face each other at a distance in the thickness direction of the insulating layer; a first electrode which is connected to the first conductor; a second electrode which is connected to the second conductor, while being arranged at a position that is away from the first electrode when viewed from the thickness direction of the insulating layer; a passivation layer which is formed on the surface of the insulating layer; a low dielectric constant layer which is formed on the surface of the passivation layer, and has a lower dielectric constant than the passivation layer; and a mold resin which covers the low dielectric constant layer.

A semiconductor device includes a bottom die including a first semiconductor layer, and a first redistribution layer (RDL) disposed on a bottom surface of the first semiconductor layer; a top die disposed on a top surface of the first semiconductor layer and including a second semiconductor layer, and a second RDL disposed on the top surface of the first semiconductor layer; a stress control (SC) layer disposed on the top surface of the first semiconductor layer and side surfaces of the top die; and a dielectric layer disposed on the SC layer, wherein the SC layer is configured to apply a compressive stress of at least 100 MPa to the top surface of the first semiconductor layer, or the SC layer is configured to apply a tensile stress of at least 100 MPa to the top surface of the first semiconductor layer.

A method of manufacturing a structure for power electronics which includes epitaxially growing a GaN semiconductor layer is provided. The method includes growing buffer layers formed of AlN and Al.sub.xGa.sub.(1-x)N, wherein 0<x<1, on a Si substrate before growing the semiconductor layer on the buffer layers. The method also includes growing deformation compensation layers formed of SiO.sub.2, SiC.sub.xN.sub.(1-x), SiN, SiC.sub.xO.sub.(1-x), SiC, SiN.sub.xO.sub.(1-x), Al.sub.2O.sub.3, and/or Cr.sub.2O.sub.3, wherein 0<x<1, on the substrate opposite the semiconductor layer. The deformation compensation layers compensate for deformation of the structure that occurs while growing the semiconductor and buffer layers and deformation that occurs while cooling the structure. The method further includes estimating epitaxial growth stress, interface stress, and thermal stress of the structure, and adjusting the temperature and or thickness of the layers based on the estimated epitaxial growth stress, interface stress, and/or thermal stress.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die; a second die and a third die having a first surface and an opposing second surface, where the first surface of the second die is electrically coupled to the first die by interconnects and the first surface of the third die is electrically coupled to the first die by a bonding material, and the bonding material includes titanium, tantalum, gold, ruthenium, silver, aluminum and nitrogen, silicon and oxygen, silicon and nitrogen, or silicon, carbon, and nitrogen; a first material, around the second die and the third die, having a non-planar surface; and a second material, on the non-planar surface of the first material and on the second and third dies, having a thermal conductivity greater than 10 watt per meter-kelvin (W/m-K) and a thickness between 1 micron and 2 microns.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a surface; a second die having a first surface, an opposing second surface, and side surfaces between the first surface and the second surface, wherein the first surface of the second die is electrically coupled to the surface of the first die, and wherein the side surfaces of the second die are scalloped. In some embodiments, side surfaces of the second die may include a protective coating material, where the protective coating material includes an alkyl silane, a fluoroalkyl silane, a thiol, a phosphonic acid, an alkanoic acid, a siloxane, a silazane, a polyolefin, or a fluorinated polymer. In some embodiments, a microelectronic assembly may further include a dielectric material around a plurality of second dies and the dielectric material does not have an interface seam.