Deformation compensation method for growing thick galium nitride on silicon substrate

Abstract

A method of manufacturing a structure for power electronics which includes epitaxially growing a GaN semiconductor layer is provided. The method includes growing buffer layers formed of AlN and Al.sub.xGa.sub.(1-x)N, wherein 0<x<1, on a Si substrate before growing the semiconductor layer on the buffer layers. The method also includes growing deformation compensation layers formed of SiO.sub.2, SiC.sub.xN.sub.(1-x), SiN, SiC.sub.xO.sub.(1-x), SiC, SiN.sub.xO.sub.(1-x), Al.sub.2O.sub.3, and/or Cr.sub.2O.sub.3, wherein 0<x<1, on the substrate opposite the semiconductor layer. The deformation compensation layers compensate for deformation of the structure that occurs while growing the semiconductor and buffer layers and deformation that occurs while cooling the structure. The method further includes estimating epitaxial growth stress, interface stress, and thermal stress of the structure, and adjusting the temperature and or thickness of the layers based on the estimated epitaxial growth stress, interface stress, and/or thermal stress.

Claims

1. A method of manufacturing a structure, comprising the steps of: applying a semiconductor layer to a substrate; the semiconductor layer being formed of gallium nitride (GaN), and the substrate being formed of a silicon-based material; applying at least one deformation compensation layer to the substrate opposite the semiconductor layer; the at least one deformation compensation layer being formed of at least one of SiO.sub.2, SiC.sub.xN.sub.(1-x), SiN, SiC.sub.xO.sub.(1-x), SiC, SiN.sub.xO.sub.(1-x), Al.sub.2O.sub.3, and Cr.sub.2O.sub.3, wherein 0<x<1; estimating at least one of (a) an epitaxial growth stress, (b) an interface stress, and (c) a thermal stress of the substrate and each of the semiconductor layer and the at least one deformation compensation layer at a selected temperature and a selected thickness before, during, or after the steps of applying the semiconductor layer and applying at least one deformation compensation layer; and determining the temperature at which the semiconductor layer and the at least one deformation compensation layer will be applied and/or the thickness of the semiconductor layer and the at least one deformation compensation layer to be applied based on at least one of the estimated epitaxial growth stress, the estimated interface stress, and the estimated thermal stress; wherein the estimated thermal stress is determined by applying the following equations for each of the substrate, the semiconductor layer, and the at least one deformation compensation layer: $\left\{\right\}={\left[D\right]}^{-1}\left\{\right\}+\left\{{}^{\mathrm{th}}\right\},\left\{{}^{\mathrm{th}}\right\}=a_{e}T=a_e\left(T-T_{\mathrm{ref}}\right),\mathrm{and}\left\{\right\}=\left[D\right]\left\{\right\},$ where {} is overall strain, {.sup.th} is thermal strain, .sub.e is a material coefficient of thermal expansion (CTE), T is a selected temperature, T.sub.ref is a reference temperature, [D] is a strain-stress matrix, and {} is a stress matrix.

2. The method according to claim 1, wherein the step of applying the semiconductor layer includes epitaxial growing of the GaN on the substrate.

3. The structure according to claim 1, wherein the semiconductor layer has a thickness ranging from greater than 1 micrometer (m) to 1000 m.

4. The method according to claim 1, wherein deformation of the structure is not greater than 450 m when the structure has a diameter ranging from 150 mm to 200 mm.

5. The method according to claim 1 including applying at least one buffer layer between the substrate and the semiconductor layer, wherein the at least one buffer layer includes at least one of AlN and Al.sub.xGa.sub.(1-x)N, wherein 0<x<1.

6. The method according to claim 1, wherein deformation of the at least one deformation compensation layer which occurs during the steps of applying the semiconductor layer and the at least one deformation compensation layer compensates for deformation of the semiconductor layer and any buffer layers located between the semiconductor layer and the substrate which occurs during the steps of applying the semiconductor layer, the at least one deformation compensation layer, and the buffer layers.

7. A structure formed according to the method of claim 1, the structure comprising: a substrate formed of a silicon-based material, the substrate having a plastic deformation limitation; a semiconductor layer disposed on the substrate, the semiconductor layer being formed of gallium nitride (GaN) and having a thickness ranging from greater than 1 m to 1000 m; and the structure, including the semiconductor layer and the substrate together, having a total deformation of less than the plastic deformation limitation of the substrate.

8. The structure according to claim 7 including at least one deformation compensation layer disposed on the substrate opposite the semiconductor layer, the at least one deformation compensation layer being formed of at least one of SiO.sub.2, SiC.sub.xN.sub.(1-x), SiN, SiC.sub.xO.sub.(1-x), SiC, SiN.sub.xO.sub.(1-x), Al.sub.2O.sub.3, and Cr.sub.2O.sub.3, wherein 0<x<1.

9. The structure according to claim 8, wherein the at least one deformation compensation layer includes a first deformation compensation layer formed of at least one of SiN, SiC.sub.xO.sub.(1-x), SiC, SiN.sub.xO.sub.(1-x), Al.sub.2O.sub.3, and Cr.sub.2O.sub.3, wherein 0<x<1; and the at least one deformation compensation layer includes a second deformation compensation layer disposed on the first deformation compensation layer and being formed of at least one of SiO.sub.2 and SiC.sub.xN.sub.(1-x), wherein 0<x<1.

10. The structure according to claim 9, wherein the first deformation compensation layer is formed of SiN and the second deformation compensation layer is formed of SiO.sub.2.

11. The structure according to claim 7 including at least one buffer layer disposed between the substrate and the semiconductor layer, wherein the at least one buffer layer includes at least one of AlN and Al.sub.xGa.sub.(1-x)N, wherein 0<x<1.

12. The structure according to claim 11, wherein the at least one buffer layer includes a first buffer layer formed of AlN and a second buffer layer formed of Al.sub.xGa.sub.(1-x)N, wherein 0<x<1.

13. The structure according to claim 7, wherein the total deformation of the structure is not greater than 450 m when the structure has a diameter ranging from 150 mm to 200 mm.

14. The structure according to claim 13, wherein the total deformation of the structure is not greater than 350 m when the structure has a diameter ranging from 150 mm to 200 mm.

15. The structure according to claim 13 including at least one buffer layer disposed between the substrate and the semiconductor layer, wherein the at least one buffer layer includes at least one of AlN and Al.sub.xGa.sub.(1-x)N, wherein 0<x<1.

16. The method according to claim 1, wherein the structure, including the semiconductor layer, the at least one deformation compensation layer, and the substrate together, has a total deformation which is less than a plastic deformation limitation of the substrate.

17. A method of manufacturing a structure, comprising the steps of: applying a semiconductor layer to a substrate; the substrate being formed of a silicon-based material and the semiconductor layer being formed of GaN; and estimating at least one of an epitaxial growth stress, an interface stress, and a thermal stress of the substrate, the semiconductor layer, and any other layers of the structure at a selected temperature and a selected thickness before, during, or after applying the layers to the substrate; and determining the temperature at which the semiconductor layer, and any other layers will be applied and/or the thickness of the semiconductor layer, and any other layers to be applied based on at least one of the estimated epitaxial growth stress, the estimated interface stress, and the estimated thermal stress, wherein the estimated thermal stress is determined by applying the following equations for the substrate, the semiconductor layer, and any other layers: $\left\{\right\}={\left[D\right]}^{-1}\left\{\right\}+\left\{{}^{\mathrm{th}}\right\},\left\{{}^{\mathrm{th}}\right\}=a_{e}T=a_e\left(T-T_{\mathrm{ref}}\right),\left\{\right\}=\left[D\right]\left\{\right\},$ where {} is overall strain, {.sup.th} is thermal strain, .sub.e is a material coefficient of thermal expansion (CTE), T is a selected temperature, T.sub.ref is a reference temperature, [D] is a strain-stress matrix, and {} is a stress matrix.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a structure including a substrate, semiconductor layer, buffer layers, and deformation compensation layers according to an example embodiment;

(2) FIG. 2 shows a general modeling structure for calculating stress in the substrate and layers during the process of manufacturing the structure according to an example embodiment;

(3) FIG. 3 a schematic plot of a two-dimensional finite element analysis (FEA) thermomechanical model;

(4) FIG. 4 is a flow chart of a numerical procedure of the FEA model;

(5) FIG. 5 shows a structure including a substrate, semiconductor layer, and buffer layers according to an example embodiment;

(6) FIG. 6 includes additional design and growth condition information and results of a simulation;

(7) FIG. 7 summarizes bow magnitude at 700 C. of experiments and simulations for various GaN thicknesses;

(8) FIG. 8 is a graph showing deformation resulting from growth of a semiconductor layer formed of a GaN on a Si substrate according to an example embodiment;

(9) FIG. 9 is a graph showing deformation resulting from growth of a deformation compensation layer formed of a SiN on a Si substrate according to an example embodiment;

(10) FIG. 10 is a graph showing deformation resulting from growth of a deformation compensation layer formed of a SiO.sub.2 on a Si substrate according to an example embodiment; and

(11) FIG. 11 is a graph showing deformation resulting from growing a semiconductor layer, buffer layers, and deformation compensation layers on a substrate according to an example embodiment.

DETAILED DESCRIPTION

(12) Embodiments of the present disclosure are described herein. It is to be understood, however, that the disclosed embodiments are merely examples and other embodiments can take various and alternative forms. The figures are not necessarily to scale; some features could be exaggerated or minimized to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the embodiments. As those of ordinary skill in the art will understand, various features illustrated and described with reference to any one of the figures can be combined with features illustrated in one or more other figures to produce embodiments that are not explicitly illustrated or described. The combinations of features illustrated provide representative embodiments for typical applications. Various combinations and modifications of the features consistent with the teachings of this disclosure, however, could be desired for particular applications or implementations.

(13) According to one embodiment, a method of manufacturing a structure 10 for use in power electronics, and more specifically a wafer including a semiconductor layer 12 formed of gallium nitride (GaN) disposed on a substrate 14 formed of a silicon (Si)-based material, is provided. The method is capable of manufacturing wafers having a GaN semiconductor layer 12 ranging from greater than 1 m to 1000 m in thickness without detrimental deformation, damage, or cracks in the GaN semiconductor layer 12. Any deformation present in the structure 10 formed by the method is less than the plastic deformation limitation of the substrate 14.

(14) The Si-based material which is used to form the substrate 14 is preferably silicon, but can be Sapphire or silicon carbide. The substrate 14 has a thickness ranging from 30 m to 1500 m, more typically, 500 m to 1500 m, for example 900 m to 1100 m or 1000 m.

(15) The step of applying the semiconductor layer 12 to the substrate 14 includes epitaxial growth of the GaN on the substrate 14. The GaN is typically applied, deposited or grown on the substrate 14 at a temperature ranging from 900 C. to 1100 C., or 970 C. to 1030 C. The GaN is also preferably grown until it reaches a thickness ranging from less than 1 m to greater than 50 m, for example 0.1 m to 100 m, or 1 m to 50 m, or 5 m to 15 m, for example 10 m.

(16) In attempt to mitigate some of the deformation of the structure 10, the method includes applying or growing at least one buffer layer 16a, 16b between the substrate 14 and the semiconductor layer 12. Thus, before applying the semiconductor layer 12, as described above, the method preferably includes growing the at least one buffer layer 16a, 16b on the substrate 14, and then growing the semiconductor layer 12 on the at least one buffer layer 16a, 16b. The one or more buffer layers 16a, 16b are typically grown to a total thickness ranging from less than 0.1 m to larger than 1 m, for example 0.3 to 0.7 m. The at least one buffer layer 16a, 16b is typically formed of AlN and/or Al.sub.xGa.sub.1-xN, wherein 0<x<1. For example, the method can including applying or growing a first buffer layer 16a formed of AlN on the substrate 14, and then growing a second buffer layer 16b formed of Al.sub.xGa.sub.(1-x)N, wherein 0<x<1, on the substrate 14. The first buffer layer 16a formed of AlN can be grown at a temperature ranging from 900 C. to 1100 C. or 970 C. to 1030 C., and to a thickness ranging from less than 0.1 m to larger than 1 m, or from 0.1 m to 1 m, or from 0.1 m to 0.3 m, for example a temperature of 1000 C. and 0.2 m in thickness. The second buffer layer 16b can be grown at a temperature ranging from 900 C. to 1100 C. or from 940 C. to 1000 C., and to a thickness ranging from less than 0.1 m to larger than 1 m, or from 0.1 m to 1 m, or from 0.2 to 0.4 m, for example a temperature of 970 C. and 0.3 m in thickness.

(17) The method includes heating the materials used to form the layers to the desired temperatures, for example the temperatures described above, and then applying the heated materials to form the layers. The structure including all of the layers is typically cooled after growing all of the layers. The layers and substrate are typically cooled to room temperature, or a temperature ranging from 15 to 25 C., for example 20 C.

(18) During the steps of applying the layers and cooling the structure 10, the substrate 14, any buffer layers 16a, 16b, and the semiconductor layer 12 experience some deformation. As explained above, the deformation of the structure 10 should be minimized in order to avoid damage or cracks in the GaN semiconductor layer 12, which could impair the performance of the structure 10 in the power electronic device. Any deformation present in the finished structure 10 formed by the method described herein is preferably less than the plastic deformation limitation of the substrate 14, and significant damage or cracks in the semiconductor layer 12 is avoided.

(19) The deformation that occurs in the substrate 14 and layers 12, 16a, 16b corresponds to stress present in the substrate 10 and layers 12, 16a, 16b. More specifically, the deformation can be determined based on the stress. Factors that affect stress evolution inside the structure 10 include (a) thermal stress, which mainly comes from nonhomogeneous thermal expansion coefficients under the influence of temperature variation; (b) growth stress, which is closely related to microstructure evolution of the layers 12, 16a, 16b closely related to microstructure evolution of the layers 12, 16a, 16b during the material deposition process; and (c) interface stress, which comes from lattice mismatch between materials of the layers 12, 16a, 16b and substrate 14.

(20) To accurately capture the stress evolution process during the method of manufacturing the structure, all the three stress sources should be considered. For the heating and cooling steps, the thermal stress is the dominate stress that can cause a structural response. For the growth process at a steady-state temperature, the microstructure evolution related growth stress and interface lattice mismatch stress are the dominate factors that affect the structural response.

(21) Before, during, or after applying at least a portion of the at least one buffer layer 16a, 16b and/or the semiconductor layer 12 to the substrate 14, the method can include estimating at least one of epitaxial growth stress, interface stress, and thermal stress of the substrate 14 and of each of the layers 12, 16a, 16b at a selected temperature and a selected thickness. The stress of the structure 10 corresponds to the deformation of the structure 10, and thus the deformation of the structure 10 can be determined based on the various stress levels. The temperature at which the layers 12, 16a, 16b will be applied during the remainder of the process or during a future process can be based on the estimated epitaxial growth stress, the estimated interface stress, and/or the estimated thermal stress. The thickness of the layers 12, 16a, 16b to be grown during the present process or a future process can also be based on at least one of the estimated epitaxial growth stress, the estimated interface stress, and the estimated thermal stress.

(22) The estimated epitaxial growth stress can be determined by a theoretical calculation, and the estimated interface stress is determined by a lattice constant at the selected temperature. The estimated thermal stress present in the structure can be determined by applying the following equations to each of the substrate 14 and layers 12, 16a, 16b:

(23) $\begin{array}{cc}\left\{\right\}={\left[D\right]}^{-1}\left\{\right\}+\left\{{}^{\mathrm{th}}\right\}& \mathrm{Equation}1\end{array}$$\begin{array}{cc}\left\{{}^{\mathrm{th}}\right\}=a_{e}T=a_e\left(T-T_{\mathrm{ref}}\right)& \mathrm{Equation}2\end{array}$$\begin{array}{cc}\left\{\right\}=\left[D\right]\left\{\right\}& \mathrm{Equation}3\end{array}$
where {} is overall strain, {.sup.th} is thermal strain, .sub.e is a material coefficient of thermal expansion (CTE), T is a selected temperature, T.sub.ref is a reference temperature, [D] is a strain-stress matrix, and {} is a stress matrix.

(24) The method can also include adjusting the temperature at which at least one of the layers 12, 16a, 16b is applied and/or the thickness of at least one of the layers 12, 16a, 16b based on at the estimated epitaxial growth stress, the estimated interface stress, and/or the estimated thermal stress.

(25) According to one embodiment, in order to reduce deformation present in the finished structure 10, the method includes applying at least one deformation compensation layer 18a, 18b to the substrate 14 opposite the semiconductor layer 12 and any buffer layers 16a, 16b. An example of the structure 10 including a first deformation layer 18a and a second deformation compensation layer 18b is shown in FIG. 1. The at least one deformation compensation layer 18a, 18b is typically formed of at least one of SiO.sub.2, SiC.sub.xN.sub.(1-x), SiN, SiC.sub.xO.sub.(1-x), SiC, SiN.sub.xO.sub.(1-x), Al.sub.2O.sub.3, and Cr.sub.2O.sub.3, wherein 0<x<1. The step of applying the at least one deformation compensation layer 18a, 18b includes growing the at least one deformation compensation layer 18a, 18b at a temperature ranging from 250 C. to 1200 C. and to a total thickness ranging from less than 1 m to larger than 10 m, or 1 m to 10 m, or 6 m to 10 m, for example 8 m. The method also includes cooling the deformation compensation layers 18a, 18b with the entire structure 10 after all of the layers are applied.

(26) The one or more deformation compensation layers 18a, 18b deform during the steps of applying the layers 12, 16a, 16b, 18a, 18b and cooling the structure 10. However, the temperatures, thicknesses, and materials of the layers 12, 16a, 16b, 18a, 18b used in the method are selected such that the deformation of the at least one deformation compensation layer 18a, 18b compensates for the deformation of any buffer layers 16a, 16b the substrate 14, and the semiconductor layer 12 that occurs during the steps of applying the layers 12, 16a, 16b, 18a, 18b and cooling the structure 10. The equations 1-3 described above can also be applied to the deformation compensation layers 18a, 18b.

(27) The structure 10 including the substrate 14, the semiconductor layer 12, any deformation compensation layers 18a, 18b, and any buffer layers 16a, 16b, formed by the method described herein has a total deformation which is less than a plastic deformation limitation of the substrate 14. The plastic deformation limitation of the substrate 14 typically ranges from 450 to 550 m when the structure 10 has diameter of 150 to 200 mm, and the deformation of the structure is thus typically not greater than 450 m, preferably not greater than 350 m. The deformation of the structure 10 changes depending on the diameter.

(28) According to an example embodiment, the at least one deformation compensation layer 18a, 18b includes a first deformation compensation layer 18a formed of at least one of SiN, SiC.sub.xO.sub.(1-x), SiC, SiN.sub.xO.sub.(1-x), Al.sub.2O.sub.3, and Cr.sub.2O.sub.3, wherein 0<x<1. The method can include growing the first deformation compensation layer 18a on the substrate opposite the semiconductor layer 12 at a temperature ranging from 200 to 400 C. or from 270 to 330 C., and to a thickness ranging from less than 1 to larger than 5 m, for example 2 to 5 m. For example, the first deformation compensation layer 18a can be SiN, applied at a temperature of 300 C. and grown to a thickness of 3 m.

(29) According to the example embodiment, the at least one deformation compensation layer 18a, 18b includes a second deformation compensation layer 18b formed of at least one of SiO.sub.2 and SiC.sub.xN.sub.(1-x), wherein 0<x<1. The method can including growing the second deformation compensation layer 18b on the first deformation compensation layer 18a at a temperature ranging from 900 to 1100 C. or from 970 to 1030 C., and to a thickness ranging from less than 1 m to larger than 10 m, or from 1 m to 10 m, or from 3 to 7 m. For example, the second deformation compensation layer 18b can be SiO.sub.2, applied at a temperature of 1000 C. and grown to a thickness of 5 m.

(30) The at least one deformation compensation layer 18a, 18b can be applied to the substrate 14 after applying any buffer layer 16a, 16b and the semiconductor layer 12. Alternatively, the deformation compensation layer 18a, 18b can be applied to the substrate 14 before applying any buffer layer 16a, 16b or the semiconductor layer 12. The method can also include removing at least a portion of the at least one deformation compensation 18a, 18b layer from the substrate 14 after applying all of the layers 12, 16a, 16b, 18a, 18b. For example, the deformation compensation layers 18a, 18b can be removed by etching, or they can be thermally or chemically removed, wholly or partially.

(31) According to one embodiment, the finished structure 10 includes the substrate 14 formed of the silicon-based material, and the semiconductor layer 12 formed of the GaN disposed on the substrate 14. The at least one deformation compensation layer 18a, 18b can be disposed on the substrate 14 opposite the semiconductor layer 12, and the at least one buffer layer 16a, 16b can be disposed between the substrate 14 and the semiconductor layer 12. The at least one buffer layer 16a, 16b can be formed of at least one of AlN and Al.sub.xGa.sub.(1-x)N, wherein 0<x<1. The at least one deformation compensation layer 18a, 18b can be formed of at least one of SiO.sub.2, SiC.sub.xN.sub.(1-x), SiN, SiC.sub.xO.sub.(1-x), SiC, SiN.sub.xO.sub.(1-x), Al.sub.2O.sub.3, and Cr.sub.2O.sub.3, wherein 0<x<1.

(32) As described above, the substrate 14 typically has a thickness ranging from 30 m to 1500 m, for example 1000 m. The semiconductor layer 12 typically has a thickness ranging from less than 1 m to larger than 50 m, for example 5 to 15 m, or 10 m. The at least one buffer layer 16a, 16b typically has a total thickness ranging from less than 0.1 m to larger than 1 m, or 0.1 m to 1 m, for example 0.3 to 0.7 m. The at least one deformation compensation layer 18a, 18b has a thickness ranging from less than 1 m to larger than 10 m, or 1 m to 10 m, or 6 to 10 m (or from less than 1 m to larger than 10 m), for example 8 m.

(33) According to one embodiment, the structure 10 includes the first buffer layer 16a disposed on the substrate 14 and having a thickness ranging from less than 0.1 m to larger than 1 m, for example 0.1 m to 1 m, or 0.1 to 0.3 m. The first buffer layer 16a is preferably formed of AlN and has a thickness of 0.2 m. The structure 10 also includes the second buffer layer 16b disposed on the substrate 14 between the first buffer layer 16a and the semiconductor layer 12. The second buffer layer 16b has a thickness ranging from less than 0.1 m to larger than 1 m, for example 0.1 m to 1 m, or 0.2 to 0.4 m. The second buffer layer 16b is preferably formed of Al.sub.xGa.sub.(1-x)N, wherein 0<x<1, and has a thickness of 0.3 m.

(34) According to one embodiment, the at least one deformation compensation layer 18a, 18b includes the first deformation compensation layer 18a disposed on the substrate 14 and formed of at least one of SiN, SiC.sub.xO.sub.(1-x), SiC, SiN.sub.xO.sub.(1-x), Al.sub.2O.sub.3, and Cr.sub.2O.sub.3, wherein 0<x<1. The first deformation compensation layer 18a has a thickness ranging from less than 1 m to larger than 5 m, for example 2 to 5 m. The first deformation compensation layer 18a is preferably SiN and has a thickness of 3 m. According to the example embodiment, the at least one deformation compensation layer 18a, 18b includes the second deformation compensation layer 18b disposed on the first deformation compensation layer 18a and formed of at least one of SiO.sub.2 and SiC.sub.xN.sub.(1-x), wherein 0<x<1. The second deformation compensation layer 18b has a thickness ranging from 3 to 7 m. The second deformation compensation layer 18b is preferably SiO.sub.2 and has a thickness of 5 m.

(35) The deformation compensation layers 18a, 18b, for example the SiN or SiO.sub.2, can be location based, include multiple layers, and different thicknesses. For example, the deformation compensation layers 18a, 18b can be thicker along the edges and thinner in the middle to enhance bowing behavior. In addition, growth of the deformation compensation layers 18a, 18b can be on a gradient. For example, there can be more N(O) farther from the SiSiN (SiSiO.sub.2) interface, to enhance stability. As discussed above, at least portion of the deformation compensation layers 18a, 18b may be removed in the finished structure 10.

(36) The diameter of the structure 10 can vary depending on the intended us of the structure 10, for example the specific power electronic design. However, according to one embodiment, the diameter of the structure 10 ranges from 50 to 100 millimeters (mm), for example 75 mm.

(37) As discussed above, the structure 10, including the substrate 14, the semiconductor layer 12, any buffer layer 16a, 16b, and any deformation compensation layer 18a, 18b have a total deformation which is less than a plastic deformation limitation of the substrate 14. The plastic deformation limitation of the substrate 14 typically ranges from 450 to 550 m, and thus the deformation of the structure 10 is typically not greater than 450 m, preferably not greater than 350 m.

(38) ExperimentPart I.

(39) An experiment was conducted to investigate a 3-layer simple stack configuration. The structure 10 investigated included a substrate 14 formed of silicon, a first buffer layer 16a formed of AlN, a second buffer layer 16b formed of Al.sub.xGa.sub.(1-x)N, where 0<x<1, and a semiconductor layer 12 formed of GaN. A general modeling structure was used to calculate stress occurring in the substrate and layers during the process of manufacturing the structure. This modeling structure is shown in FIG. 2. The epitaxial growth stress and interface stress was calculated by software, specially the commercial software known as STREEM AlGaN. Due to temperature variation in the epitaxial growth process, thermal stresses and distortions were generated in the structure. The thermal stress was mainly determined by finite element method simulation. Only elastic deformation was considered in this experiment. The equations 1-3 disclosed above were used to relate temperature, thermal strain and stress.

(40) A two-dimensional finite element analysis (FEA) thermomechanical model was then developed to simulate the deformation occurring in the epitaxial growth process of a layered structure. FIG. 3 shows the general technique required in the model. More specifically, FIG. 3 is a schematic plot of finite layer progressive activation and analysis for the epi-growth process. The structure 10 analyzed included a semiconductor layer 12 formed of the GaN and a substrate 14 formed of silicon. The structure 10 analyzed also included a first buffer layer 16a formed of the AlN, and a second buffer layer 16b formed of the Al.sub.0.2Ga.sub.0.8N. The finite layer progressive activation and analysis was applied to mimic the nature of a nano-scale sub-layer-wise epi-growth process. A thin sub-layer, on the top of the currently already deposited layers, was assumed to be the latest grown sub-layer and was added and activated when the corresponding growth height was reached. The growth stress for the corresponding growth height was implemented together with sub-layer activation. However, the model could not represent the actual nano-scale layer-wise epi-growth process since such process requires hundreds of thousands of nano-scale sub-layers. Only a limited number of layers was simulated. For each layer, a sub-layer was set to consist of several real nano-scale atomistic layers. Growth stress and interface stress from the theoretical calculation was implemented during the sub-layer sequential activation process.

(41) FIG. 4 is a flow chart of a numerical procedure of the FEA model. Coupled temperature-displacement elements were used for the whole model. A finer mesh was used for the epi-layers to directly incorporate the corresponding growth stress while coarser mesh was used in substrate regions away from the high stress zone. The meshing method can help to save computational time and maintain reasonable simulation accuracy.

(42) The experiment also included validation of the model disclosed above. This portion of the experiment included a simulation of the structure 10 including the semiconductor layer 12 formed of GaN, the first buffer layer 16a formed of the AlN, and the second buffer layer 16b formed of the Al.sub.0.2Ga.sub.0.8N, as shown in FIG. 5. The first buffer layer 16a formed of the AlN was deposited at 1000 C., the second buffer layer 16b formed of the Al.sub.0.2Ga.sub.0.8N was deposited at 970 C., and the semiconductor layer 12 formed of the GaN was deposited at 1000 C. The substrate 14 had a thickness of 1000 m, the semiconductor layer 12 was grown to a thickness of 1 m, the first buffer layer 16a was grown to a thickness of 0.2 m, the second buffer layer 16b was grown to a thickness of 0.3 m. After the epi-layer growth was finished, the entire structure 10 was gradually cooled down to room temperature, specifically 20 C.

(43) FIG. 6 includes additional design and growth condition information and results. The simulation results of FIG. 6 show if the wafer deforms toward the negative Y axis, it is a negative deformation and is called convex deformation; and if the wafer deforms toward the positive Y axis, it is a positive deformation and is called concave deformation. It was observed that concave deformation resulted from the AlN growth phase since tensile stress was created from the AlN epi-layer growth. The growth of Al.sub.0.2Ga.sub.0.8N and GaN led to compressive stress in epi-layers, and thus convex deformation was observed. Thermal stress due to material thermal expansion misfit at the final cooling phase caused tensile stress which helped the structure deform toward the positive direction.

(44) To validate the developed model, experiments were performed to measure the structure deformation magnitude at elevated temperatures. The finished structures (with various GaN epi-layer thicknesses) were uniformly heated up to 700 C. and the bows were recorded. The max bow deformation magnitudes, e.g. bow values between 700 C. and 20 C., were used for comparison against simulations. FIG. 7 summaries the bow magnitude at 700 C. of both experiments and simulations for various GaN thicknesses (1 m, 2 m, and 3 m), where the max error was <20%. Therefore, it was concluded that the model is valid and can be used for subsequent simulations.

(45) The next portion of the experiment utilized temperature-induced substrate deformation to compensate for the deformation occurring during the step of growing the GaN semiconductor layer. More specifically, the study investigated the effect of sequentially deposited materials with distinctive coefficients of thermal expansion (CTEs) at various temperatures on the final structure deformation.

(46) FIG. 8 is a graph showing deformation resulting from growth of a semiconductor layer formed of the GaN to a thickness of 10 m on the Si substrate having a thickness of 1 mm and a diameter of 150 mm. The buffer layers (AlN and Al.sub.0.2Ga.sub.0.8N) and growth temperatures were the same as the structures described in the experiment above. It was observed that the negative deformation which occurred during the GaN growth can reach 450 m, which is close to or exceeds the plastic deformation of the 1 mm Si substrate used in the simulation. Therefore, it was determined that the process would result in large final bow deformation after the structure cools down to room temperature.

(47) ExperimentPart II.

(48) The second part of the experiment tested pre-deformation during the GaN growth phase and post-deformation compensation during the cooling step to avoid problems associated with the plastic limitation and large final bow.

(49) The experiment included growing a high CTE deformation compensation layer formed of SiN (SiN CTE>Si CTE) on the bottom of Si substrate at a low temperature, specifically 300 C. During the cooling phase to 20 C., the deformation compensation layer generated a negative deformation thus forming a convex bow. During the heating phase which was 20 C. to the GaN growth temperature of about 1000 C., a concave bow was developed, as shown in FIG. 9. The pre-deformed positive bow was used to compensate for the negative deformation created during the GaN growth process.

(50) Next, post-deformation compensation which occurs during the cooling phase was tested. A low CTE deformation compensation layer formed of SiO.sub.2 (SiO.sub.2 CTE<Si CTE) was grown on the bottom of the Si substrate at a high temperature of 1000 C. and then the structure was cooled down to room temperature of 20 C. The thermal expansion misfit caused positive deformation thus forming a concave bow, as shown in FIG. 10. The pre-deformed positive bow was used to compensate for the deformation created during the final cooling process.

(51) Therefore, it was concluded that the correct combination of the pre-deformation compensation and the post-deformation compensation described above with a carefully chosen material thicknesses would help to mitigate the GaN growth deformation at high temperatures as well as wafer cooling deformation at low temperatures.

(52) ExperimentPart III.

(53) A simulation example was conducted to demonstrate the effectiveness of the method described above including the pre-deformation compensation and the post-deformation compensation. The structure of the simulation is shown in FIG. 1. The first buffer layer 16a formed of the AlN was deposited at 1000 C., the second buffer layer 16b formed of the Al.sub.0.2Ga.sub.0.8N was deposited at 970 C., and the semiconductor layer 12 formed of the GaN was deposited at 1000 C. The substrate 14 had a thickness of 1000 m, the semiconductor layer 12 was grown to a thickness of 10 m, the first buffer layer 16a was grown to a thickness of 0.2 m, the second buffer layer 16b was grown to a thickness of 0.3 m. In addition, first deformation compensation layer formed of SiN and having a thickness of 3 m was grown at the bottom of the Si substrate at 300 C., and a second deformation compensation layer formed of SiO.sub.2 and having a thickness of 5 m was grown at the bottom of the first deformation compensation layer at a temperature of 1000 C. The structure 10 was symmetric and had a diameter of 75 mm. The growth thicknesses and the growth temperatures disclosed herein were examples but the method is not limited to those examples. Based on availability of actual process techniques and the GaN thickness (e.g., a few m to tens of m), it was determined that the SiN growth temperature can be about 250 C. to about 400 C., and the SiO.sub.2 growth temperature can be about 800 C. to about 1000 C. It was also determined that the corresponding material thickness should be adjusted as well to achieve a reasonable deformation compensation.

(54) The simulation results showed that the deposited deformation compensation layers at the bottom of substrate helped to shift the curve of deformation caused by the GaN growth process up so that the final deformation was below the plastic limitation of the substrate. The process deformation plot is shown in FIG. 11. Specifically, at 1000 C., the deformation due to thermal mismatch contributed by 3 m thick SiN was about +220 m, which helped to shift the maximum negative deformation from about 450 m to about 250 m, which was below the Si substrate plastic deformation limitation. In addition, the deformation due to thermal mismatch contributed by the 5 m thick SiO.sub.2 helped to bring the structure to a flat level during the final cooling phase.

(55) While exemplary embodiments are described above, it is not intended that these embodiments describe all possible forms encompassed by the claims. The words used in the specification are words of description rather than limitation, and it is understood that various changes can be made without departing from the spirit and scope of the disclosure. As previously described, the features of various embodiments can be combined to form further embodiments of the invention that may not be explicitly described or illustrated. While various embodiments could have been described as providing advantages or being preferred over other embodiments or prior art implementations with respect to one or more desired characteristics, those of ordinary skill in the art recognize that one or more features or characteristics can be compromised to achieve desired overall system attributes, which depend on the specific application and implementation. These attributes can include, but are not limited to cost, strength, durability, life cycle cost, marketability, appearance, packaging, size, serviceability, weight, manufacturability, ease of assembly, etc. As such, to the extent any embodiments are described as less desirable than other embodiments or prior art implementations with respect to one or more characteristics, these embodiments are not outside the scope of the disclosure and can be desirable for particular applications.