Provided are a substrate for epitaxially growing a diamond crystal, having at least a surface made of a metal, in which the above surface made of the metal is a plane having an off angle of more than 0, and the full width at half maximum of the X-ray diffraction peak from the (002) plane by the X-ray rocking curve measurement at the above surface made of the metal is 300 seconds or less; and a method of manufacturing a diamond crystal, including epitaxially growing a diamond crystal on the above surface made of the metal of the above substrate.

Methods for depositing a boron nitride film on a substrate are disclosed. More particularly, the disclosure relates to methods that can be used for depositing a boron nitride film by a PECVD process. The method comprises providing a substrate into a reaction chamber, and executing a cyclical deposition process comprising a plurality of deposition cycles, ones from the plurality of deposition cycles including providing a boron precursor into the reaction chamber and providing a deposition plasma gas into the reaction chamber.

Provided is a method for manufacturing a semiconductor device whose electric characteristics are prevented from being varied and whose reliability is improved. In the method, an insulating film is formed over an oxide semiconductor film, a buffer film is formed over the insulating film, oxygen is added to the buffer film and the insulating film, a conductive film is formed over the buffer film to which oxygen is added, and an impurity element is added to the oxide semiconductor film using the conductive film as a mask. An insulating film containing hydrogen and overlapping with the oxide semiconductor film may be formed after the impurity element is added to the oxide semiconductor film.

A multilayer structure of the present invention is a multilayer structure including a base substrate and a semiconductor film that is made of -Ga.sub.2O.sub.3 or an -Ga.sub.2O.sub.3-based solid solution and has a corundum crystal structure, the semiconductor film being disposed on the base substrate. The semiconductor film has an average film thickness of greater than or equal to 10 m. The semiconductor film is convexly or concavely warped. An amount of warpage of the semiconductor film is 20 m or greater and 64 m or less.

A SiC epitaxial wafer according to an embodiment includes a SiC substrate, and a SiC epitaxial layer on one surface of the SiC substrate. The SiC epitaxial layer has a buffer layer and a drift layer. The buffer layer is located between the drift layer and the SiC substrate, and has an impurity concentration higher than an impurity concentration of the drift layer. The impurity concentration of the buffer layer is 2.010.sup.18 cm.sup.3 or more. In a case where the impurity concentration at a center in plan view in a laminating direction is measured in the laminating direction, uniformity of the impurity concentration in the buffer layer is 50% or less.

A semiconductor device includes a gate structure, two recesses and two epitaxial layers. The gate structure is disposed on a substrate. The two recesses are disposed in the substrate and at two sides of the gate structure. Each of the recesses includes a first inclined surface, a second inclined surface and a third inclined surface connected sequentially from bottom to top. The first inclined surface and the second inclined surface define a first tip structure therebetween. The second inclined surface and the third inclined surface define a second tip structure therebetween. The two epitaxial layers are respectively disposed in the two recesses.

Deep trench isolation structures for high voltage semiconductor-on-insulator devices are disclosed herein. An exemplary deep trench isolation structure surrounds an active region of a semiconductor-on-insulator substrate. The deep trench isolation structure includes a first insulator sidewall spacer, a second insulator sidewall spacer, and a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer. The multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom silicon portion. The bottom polysilicon portion is formed by a selective deposition process, while the top polysilicon portion is formed by a non-selective deposition process. In some embodiments, the bottom silicon portion is doped with boron.

A method for growing a III-V material may include forming at least one layer on a stack including a crystalline layer made of III-V material, a first masking layer surmounting the germination layer, the first masking layer having at least one first opening; depositing a second masking layer covering an upper face of the sacrificial layer; forming at least one second opening in the second masking layer; removing the sacrificial layer selectively at the first masking layer and at the second masking layer; epitaxially growing a material made of the III-V material from the germination layer; forming al least one third opening in the second masking layer; and epitaxially growing at least one material made of the III-V material from the first epitaxial layer.

The present disclosure describes a method that mitigates the formation of facets in source/drain silicon germanium (SiGe) epitaxial layers. The method includes forming an isolation region around a semiconductor layer and a gate structure partially over the semiconductor layer and the isolation region. Disposing first photoresist structures over the gate structure, a portion of the isolation region, and a portion of the semiconductor layer and doping, with germanium (Ge), exposed portions of the semiconductor layer and exposed portions of the isolation region to form Ge-doped regions that extend from the semiconductor layer to the isolation region. The method further includes disposing second photoresist structures over the isolation region and etching exposed Ge-doped regions in the semiconductor layer to form openings, where the openings include at least one common sidewall with the Ge-doped regions in the isolation region. Finally the method includes growing a SiGe epitaxial stack in the openings.

Provided are high quality metal-nitride, such as aluminum nitride (AlN), films for heat dissipation and heat spreading applications, methods of preparing the same, and deposition of high thermal conductivity heat spreading layers for use in RF devices such as power amplifiers, high electron mobility transistors, etc. Aspects of the inventive concept can be used to enable heterogeneously integrated compound semiconductor on silicon devices or can be used in in non-RF applications as the power densities of these highly scaled microelectronic devices continues to increase.