A semiconductor device includes a lower structure, a data storage structure on the lower structure, and an inductor structure on the lower structure, where the data storage structure includes first electrodes extending in a vertical direction perpendicular to an upper surface of the lower structure, a second electrode provided on the first electrodes, and a dielectric layer between the first electrodes and the second electrode, and where the inductor structure includes an inductor conductive pattern at a level that is substantially the same as a level of the first electrodes.

This disclosure relates to embodiments that include an apparatus that may comprise a first layer including a first plurality of active devices, a second layer including a second plurality of active devices, and/or a third layer including a plurality of passive devices and disposed between the first and the second layers. An active device of the first plurality of active devices and an active device of the second plurality of active devices may influence a state of charge of a passive device of the plurality of passive devices.

A solid state circuit breaker structure and electronic switching circuit is provided. The solid state circuit breaker structure includes a power substrate, a power die, a plurality of bond wires, and a magnetic body. The power die is mounted on the power substrate. The bond wires extend outwardly from the power die. The magnetic body is attached to the power substrate and disposed to increase a magnetic field produced by a current flowing through the bond wires and thereby produce a first inductance that produces a decrease in an overvoltage at turn off of the power die.

An integrated circuit device, having a first number of terminals, and a first plurality of functional circuits including a second number of functional circuits requiring access to the terminals in the first number of terminals, where the second number is greater than the first number, includes a second plurality of functional circuits from among the first plurality of functional circuits, the second plurality of functional circuits sharing access to a shared terminal among the first number of terminals, and a respective isolation circuit between the shared terminal among the first number of terminals and each respective functional circuit in the second plurality of functional circuits, the respective isolation circuit being configured to prevent coupling of noise from one respective functional circuit in the second plurality of functional circuits to another respective functional circuit in the second plurality of functional circuits via the shared terminal.

An inductor device includes a pattern ground shield (PGS) structure, a first trace, a second trace, and a first center-tapped element. The first trace is disposed above the pattern ground shield structure, and located in a first area. The second trace is disposed above the pattern ground shield structure, and located in a second area. The first area is adjacent to the second area. The first center-tapped element is disposed above the first trace or below the first trace, and passes through a first center point of the first area.

An isolator includes a substrate; a first insulating film on the substrate; a second insulating film on the first insulating film, a third insulating film on the second insulating film, a first interconnect in the second insulating film, and first and second coils. The first interconnect has a thickness equal to a film thickness of the second insulating film. The first coil extends in the first and second insulating films. The first coil has a length in the extending direction greater than the thickness of the first interconnect. The third insulating film is provided on the second insulating film, and covers the first interconnect and the first coil. The second coil is provided on the third insulating film, and faces the first coil via the third insulating film.

A microelectronic device includes a memory array region, an interconnect region, and a control logic region. The memory array region includes a stack structure including tiers each including conductive material and insulative material vertically neighboring the conductive material and conductive routing overlying the stack structure. The interconnect region underlies the memory array region and includes connected bond pads. The control logic region underlies the interconnect region and comprises control logic devices to effectuate control operations for the microelectronic device. The microelectronic device may also include a conductive loop assembly extending, in a looped path, through each of the memory array region, the interconnect region, and the control logic region.

In an integrated circuit device, a first first-type transistor and a first second-type transistor are stacked with each other at the front side of a substrate, and a second first-type transistor and a second second-type transistor are also stacked with each other at the front side of the substrate. The integrated circuit device also includes a front-side inductor having one or more conductors in a front-side upper metal layer at the front side of the substrate, and a back-side inductor having one or more conductors in a back-side lower metal layer at a back side of the substrate. The front-side inductor and the back-side inductor are conductively connected in series and forms a combined inductor. The front-side inductor, the first first-type transistor, and the first second-type transistor form a stack directly above the back-side inductor.

An embedded inductor may include a substrate. The inductor may include a first layer of magnetic film, disposed on a first side of the substrate. The inductor may include a second layer of magnetic film, disposed on a second side of the substrate. The inductor may include a dielectric layer disposed over each of the first and second layers of magnetic film may include. The inductor may include a first redistribution layer formed over the dielectric layer. The inductor may include a second redistribution layer a formed over the dielectric layer. The inductor may include two or more through-substrate vias (TSVs) extending through the dielectric layer and the substrate from the first redistribution layer to the second redistribution layer.

An electronic device, includes (a) a semiconductor substrate, (b) a plurality of transistors formed on a first side of the semiconductor substrate, and (c) a first set of metal interconnect layers formed on the first side of the semiconductor substrate, and a second set of metal interconnect layers formed on a second side of the semiconductor substrate opposite to the first side, each of the first set and the second set of metal interconnect layers includes (i) one or more layers whose electrical resistance is in a first range of resistances, and (ii) at least one layer whose electrical resistance is in a second range of resistances, lower than the first range.