A power module includes a substrate having first and second surfaces and first, second, and third metal interconnects. A semiconductor die on the first surface is coupled to the first metal interconnect. An encapsulation material has third and fourth opposing surfaces. The third surface is on the second surface. Primary inductors in the encapsulation material have a first lateral segment, a first vertical segment extending between a first end of the first lateral segment and the third surface, and a second vertical segment extending from a second end of the first lateral segment to the fourth surface. Secondary inductors have a second lateral segment and third and fourth vertical segments extending from ends of the second lateral segment to the third surface. A pair of adjacent third vertical segments are coupled via the second metal interconnect. A pair of adjacent fourth vertical segments are coupled via the third metal interconnect.

A laminated wiring has a first conductor which connects first terminals of one or more capacitors and each positive terminal of a plurality of semiconductor modules, a second conductor which connects second terminals of the one or more capacitors and each negative terminal of the plurality of semiconductor modules, and an insulator. Slits are cut in at least one of the first conductor and the second conductor (in both of them in the example of FIG. 1). By doing so, among the plurality of semiconductor modules, a variation in the total of respective inductance values between respective first terminals and one positive terminal closest to the respective first terminals and respective inductance values between respective negative terminals to one second terminal closest to the respective negative terminals becomes smaller than or equal to 10 nH.

A semiconductor device includes lower circuit patterns on a lower substrate; lower bonding patterns on the lower circuit patterns, the lower bonding patterns including a conductive material and being electrically connected to the lower circuit patterns; upper bonding patterns on and contacting the lower bonding patterns, and including a conductive material; a passive device on the upper bonding patterns, and including a conductive material and contacting one of the upper bonding patterns; a gate electrode structure on the passive device, and including gate electrodes spaced apart from each other in a first direction, each of which extends in a second direction, and extension lengths in the second direction of the gate electrodes increasing from a lowermost level toward an uppermost level in a stepwise manner; a channel extending through at least a portion of the gate electrode structure; and an upper substrate on the channel.

A structure includes a substrate having a frontside and a backside. A first electrode is in a first insulator layer and is adjacent to the frontside of the substrate. The first electrode is part of a redistribution layer (RDL). A second electrode is between the substrate and the first electrode. A dielectric-filled trench in the substrate is under the first electrode and the second electrode, the dielectric-filled trench may extend fully to the backside of the substrate. The structure provides a galvanic isolation that exhibits less parasitic capacitance to the substrate from the lower electrode.

A microelectronic device including a beveled interconnect is disclosed. Example microelectronic devices include a dielectric layer having a first surface at a first height over a substrate, a second surface at a second height over the substrate, and a third surface connecting the first surface and the second surface. The first and third surfaces form a beveled corner. A beveled interconnect includes a first interconnect segment over the first surface and a second interconnect segment extending from the first interconnect segment toward the second surface and ending over the third surface.

A storage device includes a substrate of a memory package and a first memory die. The substrate includes a controller and a first pin pad, the first pin pad being electrically connected to the controller and defining a data channel for data communications. The first memory die includes a front pin pad electrically connected to the first pin pad of the substrate by way of a first bond wire, a rear pin pad, a redistribution layer electrically connecting the front pin pad and the rear pin pad of the first memory die, and a plurality of memory cells configured to provide non-volatile storage accessible by way of the data channel.

An integrated circuit includes a semiconductor substrate and a plurality of dielectric layers over the semiconductor substrate, including a top dielectric layer. A metal plate or metal coil is located over the top dielectric layer; a metal ring is located over the top dielectric layer and substantially surrounds the metal plate or metal coil. A protective overcoat overlies the metal ring and overlies the metal plate or metal coil. A trench opening is formed through the protective overcoat, with the trench opening exposing the top dielectric layer between the metal plate/coil and the metal ring, the trench opening substantially surrounding the metal plate or metal coil.

An isolated power chip based on wafer level packaging, including: an RDL-based micro-transformer, where a primary coil of the RDL-based micro-transformer is connected to a direct-current power supply and configured to output a direct-current voltage input by the direct-current power supply; a transmitting chip connected to the primary coil of the RDL-based micro-transformer, and configured to receive the direct-current voltage, convert the direct-current voltage into an alternating current signal, and transmit the alternating current signal to a secondary coil of the RDL-based micro-transformer; and a receiving chip connected to the secondary coil of the RDL-based micro-transformer, and configured to convert the alternating current signal into a direct-current signal, generate a control signal for stabilizing the output voltage according to a change of a load, and encode the control signal for digital isolation. The present disclosure further provides a method of manufacturing an isolated power chip based on wafer level packaging.

A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer. The third patterned conductive layer is on the second patterned conductive layer, and the connector is directly on the third patterned conductive layer.

An embodiment is a device including an integrated circuit die having an active side and a back side, the back side being opposite the active side, a molding compound encapsulating the integrated circuit die, and a first redistribution structure overlying the integrated circuit die and the molding compound, the first redistribution structure including a first metallization pattern and a first dielectric layer, the first metallization pattern being electrically coupled to the active side of the integrated circuit die, at least a portion of the first metallization pattern forming an inductor.