A semiconductor package is provided. The semiconductor package includes a first die and a second die bonded to the first die. An encapsulant laterally encapsulates the second die. Through vias are disposed in the encapsulant. An interconnect structure is disposed on the second die, the through vias and the encapsulant. A redistribution structure is disposed on the interconnect structure. An inductor is embedded in the redistribution structure and the interconnect structure, wherein the inductor includes a portion of a metallization pattern of the redistribution structure and a portion of a conductive pattern of the interconnect structure. The portion of the metallization pattern of the inductor is adjacent to and substantially overlapped with the portion of the conductive pattern of the inductor. A manufacturing method of a semiconductor package is also provided.

Disclosed is a structure and a method of forming the structure. The structure includes first and second semiconductor substrates with adjacent surfaces (e.g., bonded surfaces), a first spiral-shape metallic feature in the first semiconductor substrate, and a second spiral-shaped metallic feature in the second semiconductor substrate. The second spiral-shaped metallic feature is aligned above and electrically connected to the first spiral-shaped metallic feature. In some embodiments, the second spiral-shaped metallic feature is stacked on and immediately adjacent to the first spiral-shaped metallic feature at the bonded surfaces, thereby forming a relatively large inductor with high Q.sub.dc in a relatively small area. In other embodiments, the first and second spiral-shaped metallic features are discrete inductors located on opposite sides of the semiconductor substrates from the bonded surfaces but electrically connected in parallel (e.g., using stacked TSVs), effectively forming a relatively large inductor with a high Q.sub.dc in a relatively small area.

A device package includes a first tier, a second tier stacked upon the first tier, and a through tier via unitarily penetrating through the first and second tiers. The first tier includes a first device and a first interconnect structure electrically coupled to the first device, the first interconnect structure includes a first metal layer, and the first metal layer includes a first connection branch. The second tier includes a second device and a second interconnect structure electrically coupled to the second device, the second interconnect structure includes a second metal layer, and the second metal layer includes a second connection branch. The through tier via is electrically coupled to the first and second connection branches.

Embodiments of the invention include providing interconnects with two-dimensional free zero line end enclosure. A first metal line is formed. A second metal line is connected by a via to the first metal line, the first metal line having a first end with a zero line extension in relation to the via in a first dimension, the second metal line having another first end with a zero line extension in relation to the via in a second dimension perpendicular to the first dimension.

The present disclosure provides a semiconductor structure and a fabrication method thereof. The semiconductor structure includes: a base, wherein the base is provided with a first surface and a second surface that are opposite to each other; a magnetic core, wherein the magnetic core is located in the base, and an orthographic projection of the magnetic core on the first surface is a closed ring pattern; a dielectric layer, wherein the dielectric layer is located on the second surface; and a solenoid-shaped metal layer, wherein the metal layer is located in the base and the dielectric layer and is wound around the magnetic core; the metal layer is an integrated structure; the metal layer and the magnetic core are spaced apart from each other; part of the metal layer is exposed on the first surface.

A transformer device includes: a planar first coil; a first insulation layer being provided above the first coil; an intermediate layer being provided above the first insulation layer; a second insulation layer being provided above the intermediate layer; a planar second coil being provided above the second insulation layer and facing the first coil; and a pad having conductivity being provided above the second insulation layer and being connected to one end side of the second coil. The pad is disposed at a position at least partially overlapping the intermediate layer in plan view. The intermediate layer has hardness higher than hardness of the first insulation layer and the second insulation layer.

The present disclosure provides a semiconductor package structure, relating to the technical field of semiconductors. The semiconductor package structure includes: a substrate; and at least one chip stack structure provided on the substrate, where the at least one chip stack structures include a plurality of first chips vertically stacked, each of the first chips includes a first conductive plug set, a connection layer is provided between two adjacent first chips, a wire structure is provided in the connection layer, the wire structure is electrically connected to the first conductive plug sets in two first chips adjacent to the wire structure, projections of two first conductive plug sets electrically connected to a same wire structure on the substrate are staggered from each other, and the first conductive plug sets in the plurality of first chips are connected in series through the wire structures to form an inductor structure.

A semiconductor chip includes a lower wiring layer, a multilayer wiring layer formed on the lower wiring layer, and an upper wiring layer formed on the multilayer wiring layer. Here, a thickness of a wiring provided in the lower wiring layer is larger than a thickness of each of a plurality of wirings provided in the multilayer wiring layer, and a thickness of a wiring provided in the upper wiring layer is larger than the thickness of each of the plurality of wirings provided in the multilayer wiring layer. A lower inductor which is a component of a transformer is provided in the lower wiring layer, and an upper inductor which is a component of the transformer is provided in the upper wiring layer.

Embodiments herein describe an integrated circuit (IC) including an integrated circuit including a first die and a second die including an inductor and disposed over the first die, where the second die is electrically coupled to the first die via hybrid bonds (HBs). The IC may include a metal layer disposed under a portion of the inductor. The IC may further include a shielding layer disposed within the first die. The IC may also include first metal strips disposed adjacent a head section of the inductor and second metal strips disposed over a leg section of the inductor. The inductor may include a head section constructed as a dual loop and a leg section constructed as a pair of legs, where the inductor is enclosed within isolation walls.

A stacked substrate structure and a manufacturing method thereof are provided. The stacked substrate structure includes a first structure and a second structure. The first structure has a first bonding surface and includes a first circuit structure. The first circuit structure includes a plurality of first conductive layers and a first expansion modulation layer. The plurality of first conductive layers are stacked in a vertical direction. The first expansion modulation layer is disposed between the adjacent first conductive layers. A coefficient of thermal expansion of the first expansion modulation layer is greater than a coefficient of thermal expansion of the plurality of first conductive layers. The second structure has a second bonding surface, and the second bonding surface of the second structure faces the first bonding surface of the first structure.