Disclosed is a semiconductor package device comprising a lower redistribution substrate, a first semiconductor chip on the lower redistribution substrate, vertical structures on the lower redistribution substrate, and a first molding member on the lower redistribution substrate and on the first semiconductor chip and the vertical structures. The vertical structure includes a first post having a first diameter, a second post on the first post and having a second diameter, and a bonding pad on the second post opposite the first post and having a third diameter. The first, second, and third diameters are different from each other. The third diameter is greater than the second diameter.

Disclosed herein are methods of forming a microelectronic component. In some embodiments, the method includes providing an element having a metallization layer that comprises a field dielectric and a conductive feature embedded in the field dielectric. The metallization layer also comprises a surface that includes the field dielectric and the conductive feature. The method further includes forming a copper feature over the conductive feature, forming a dielectric layer over sidewalls of the copper feature, and then planarizing the dielectric layer to form a hybrid bonding surface, where the copper feature is exposed at the hybrid bonding surface.

A package structure and a formation method are provided. The method includes forming multiple patterned material elements over a carrier substrate, and the patterned material elements are more thermal conductive than copper. The method also includes forming a protective layer laterally surrounding each of the patterned material elements. The method further includes bonding a chip-containing structure to a first patterned material element of the patterned material elements through dielectric-to-dielectric bonding and metal-to-metal bonding.

Methods, systems, and devices for pass-through power delivery for logic-on-top semiconductor systems are described. A semiconductor system may be configured with a two-dimensional pattern of power delivery conductors that pass through semiconductor components of a stack (e.g., through one or more memory stacks), providing a more-distributed delivery of power to a logic component bonded with the stack. The power delivery conductors may include through-substrate vias that bypass circuitry of the stack, and thus may be allocated for providing power to the logic component. Such techniques may be combined with a redistribution component, such as a package substrate or interposer (e.g., opposite the logic component in the heterogeneous stack), which may include redistribution conductors that convert from relatively fewer interconnections at a surface of the semiconductor system (e.g., for solder interconnection) to relatively more interconnections at a surface bonded with the stack (e.g., for hybrid bonding interconnection).

A semiconductor device assembly can include a first semiconductor device comprising CMOS circuitry at a first active surface and a second semiconductor device having a footprint smaller than that of the first semiconductor device and including memory array circuitry at a second active surface hybrid-bonded to the first active surface. The assembly can further include a gapfill material directly contacting the first active surface of the first semiconductor device and having an upper surface coplanar with a back surface of the second semiconductor device, and a metallization layer disposed over the second semiconductor device and the gapfill material. The metallization layer can include conductive structures operably coupled to the second semiconductor device through back-side contacts of the second semiconductor device. The assembly can further include a plurality of bond pads disposed at an upper surface of the metallization layer and coupled to the conductive structures of the metallization layer.

A chiplet hub for interconnecting a series of connected chiplets and internal resources. An HBM is mounted on top of the chiplet hub to provide multiple party access to the HBM and to save System in Package (SIP) area. The chiplet hub can form system instances to combine connected chiplets and internal resources, with the system instances being isolated. One type of system instance is a private memory system instance with private memory gathered from multiple different memory devices. The chiplet hubs can be interconnected to form a clustered chiplet hub to provide for a larger number of chiplet connections and more complex system. A DMA controller can receive DMA service requests from devices other than a system hosted, including in cases where the chiplet hub is non-hosted.

A semiconductor package includes a redistribution structure including a wiring structure and an insulating structure covering the wiring structure, the redistribution structure having a first surface and a second surface, which are opposite to each other, the insulating structure including a polymer, a semiconductor chip on the first surface, the semiconductor chip being connected to at least one first wiring pattern in the wiring structure, a passivation insulating film covering the second surface, the passivation insulating film including an inner surface contacting the insulating structure and a hole sidewall defining a hole, the passivation insulating film including an inorganic insulating material, a conductive pad passing through the passivation insulating film via the hole and contacting the second wiring pattern, the conductive pad having a pad sidewall contacting the hole sidewall, and an external connection terminal on the conductive pad.

A semiconductor package includes a die stack including a first semiconductor die having a first interconnect structure, and a second semiconductor die having a second interconnect structure direct bonding to the first interconnect structure of the first semiconductor die. The second interconnect structure includes connecting pads disposed in a peripheral region around the first semiconductor die. First connecting elements are disposed on the connecting pads, respectively. A substrate includes second connecting elements on a mounting surface of the substrate. The first connecting elements are electrically connected to the second connecting elements through an anisotropic conductive structure.

A semiconductor package may include a first semiconductor chip and a second semiconductor chip on a top surface thereof. The first semiconductor chip may include a first bonding pad on a top surface of a first semiconductor substrate and a first penetration via on a bottom surface of the first bonding pad and penetrating the first semiconductor substrate. The second semiconductor chip may include a second interconnection pattern on a bottom surface of a second semiconductor substrate and a second bonding pad on a bottom surface of the second interconnection pattern and coupled to the second interconnection pattern. The second bonding pad may be directly bonded to the first bonding pad. A width of the first penetration via may be smaller than that of the first bonding pad, and a width of the second interconnection pattern may be larger than that of the second bonding pad.

A device package comprising an integrated cooling assembly comprising a semiconductor stack and a cooling channel, wherein the semiconductor stack comprises a first semiconductor device and a second semiconductor device stacked vertically above the first semiconductor device; and spacers extending between opposing surfaces of the first and second semiconductor devices to space the first semiconductor device away from the second semiconductor device, the spacers and the opposing surfaces of the first and second semiconductor devices collectively define the cooling channel therebetween; and the spacers comprise via electrically connecting the first semiconductor device and the second semiconductor device.