Provided is a redistribution structure having reduced parasitic capacitance. The redistribution structure may include a via layer and a wiring layer disposed on the via layer in a first direction perpendicular to the via layer, the wiring layer including a metal plate and a first insulation pattern configured to penetrate the metal plate in the first direction. An outer side surface of the first insulation pattern may be exposed from a side surface of the metal plate.

A device package comprising an integrated cooling assembly comprising a semiconductor device and a cold plate directly bonded to the semiconductor device. The cold plate comprises a top portion, sidewalls extending downwardly from the top portion to a backside of the semiconductor device, an inlet opening, and an outlet opening. The top portion, the sidewalls, and the backside of the semiconductor device collectively define a coolant chamber volume therebetween. The inlet opening and the outlet opening are disposed in the top portion and are in fluid communication with the coolant chamber volume. The inlet opening is disposed above a hotspot region of the semiconductor device.

An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

A semiconductor package includes a semiconductor chip including a semiconductor substrate having an active layer, ground chip pads on the semiconductor substrate, and signal chip pads on the semiconductor substrate and a package substrate supporting the semiconductor chip, the package substrate including a substrate insulating layer, a plurality of signal line patterns extending in the substrate insulating layer and electrically connected to the signal chip pads, and a plurality of ground line patterns extending in the substrate insulating layer at a same level as a level of the plurality of signal line patterns and electrically connected to the ground chip pads. At least one of the plurality of ground line patterns extends between the plurality of signal line patterns.

An interconnect structure includes a plurality of first pads, a plurality of second pads, and a plurality of conductive lines. The first pads are arranged to form a first column-and-row array, and the second pads are arranged to form a second column-and-row array. The first column-and-row array, the second column-and-row array and the conductive lines are disposed in a same layer. The first pads in adjacent rows in the first column-and-row array are separated from each other by a first vertical distance from a plan view, the second pads in adjacent rows in the second column-and-row array are separated from each other by a second vertical distance from the plan view. A sum of widths of the conductive lines electrically connecting the first pads and the second pads in the same row is less than the first vertical distance and the second vertical distance from the plan view.

A chip package unit, a method of manufacturing the same, and package structure formed by stacking the same are provided. At least one first connecting pad, at least one second connecting pad, and at least one third connecting pad of a flexible printed circuit (FPC) board in the chip package unit are electrically connected with one another by circuit of the FPC board. At least one die pad disposed on a front surface of a chip is electrically connected with the first connecting pad first and then electrically connected with the outside by the second connecting pad or the third connecting pad. Thereby the chip of the chip package unit can be electrically connected with the outside by the front surface or a back surface thereof. Therefore, not only production is reduced due to simplified production process and energy saved, volume of the package structure is also reduced.

An integrated circuit package structure is provided. The integrated circuit package structure includes a circuit substrate. The circuit substrate includes a core, a first inorganic dielectric layer, an organic dielectric layer and a solder mask layer. The core has a first surface and a second surface opposite each other. The first inorganic dielectric layer is disposed on the first surface of the core. The organic dielectric layer is disposed on the second surface of the core. The solder mask layer is disposed on the organic dielectric layer. The solder mask is separated from the first inorganic dielectric layer by the organic dielectric layer and the core.

In an embodiment, a device includes: a first integrated circuit die comprising a semiconductor substrate and a first through-substrate via; a gap-fill dielectric around the first integrated circuit die, a surface of the gap-fill dielectric being substantially coplanar with an inactive surface of the semiconductor substrate and with a surface of the first through-substrate via; a dielectric layer on the surface of the gap-fill dielectric and the inactive surface of the semiconductor substrate; a first bond pad extending through the dielectric layer to contact the surface of the first through-substrate via, a width of the first bond pad being less than a width of the first through-substrate via; and a second integrated circuit die comprising a die connector bonded to the first bond pad.

A semiconductor structure includes an interposer that includes: a substrate; a redistribution structure (RDS) on the substrate; a passivation film on the RDS, where the passivation film includes a first etch stop layer (ESL) on the RDS and a first dielectric layer on the first ESL; a via embedded in the passivation film, where the via is electrically coupled to a conductive feature of the RDS; a bonding film on the passivation film, where the bonding film includes a second ESL on the passivation film and a second dielectric layer on the second ESL; and a bonding pad and a first dummy bonding pad that are embedded in the bonding film, where the bonding pad is electrically coupled to the via, and the first dummy bonding pad is electrically isolated; and a die attached to the interposer, where a die connector of the die is bonded to the bonding pad.

A copper diffusion-suppressing electrical bond between a first semiconductor wafer or chip or interposer and a second semiconductor wafer or chip or interposer includes a first bond pad metal with a first bond pad metal surface disposed on the first semiconductor wafer or chip or interposer, bonded with a second bond pad metal with a second bond pad metal surface disposed on the second semiconductor wafer or chip or interposer. A copper outdiffusion-suppressing coating such as a titanium, cobalt, nickel/gold, or nickel/palladium/gold layer may be disposed on the first copper bond pad metal surface and/or on the second copper bond pad metal surface. The copper of the bond pad metal may be doped with manganese to form a copper outdiffusion-suppressing surface manganese oxide. The bond pad metal may alternatively be tungsten to prevent copper outdiffusion.