According to an example aspect of the present invention, there is provided a wafer-level package (1), comprising a top substrate (10) and a bottom substrate (30), wherein the top substrate (10) comprises a recess (12) on a side of the top substrate (10) which is towards the bottom substrate (30) and the bottom substrate (30) comprises a recess (32) on a side of the bottom substrate (30) which is towards the top substrate (10), wherein the recess (12) of the top substrate (10) and the recess (32) of the bottom substrate (30) are arranged to form a waveguide (5) within the wafer-level package (1) and a middle substrate (20) arranged to couple an integrated circuit (24) of the wafer-level package (1) to the waveguide (5), wherein the middle substrate (20) is in between the top substrate (10) and the bottom substrate (30) and the middle substrate (20) comprises a probe (21), wherein the probe (21) extends to the waveguide (5) and the probe (21) is arranged to couple a signal coming from the integrated circuit (24) to the waveguide (5), or to couple a signal coming from the waveguide (5) to the integrated circuit (24).

According to an example aspect of the present invention, there is provided a bonding structure for forming at least one electrical connection between an optoelectronic component and a photonic substrate. The bonding structure comprises a pillar structure between the optoelectronic component and the photonic substrate, and a bonding layer comprising bonding material on the pillar structure. The pillar structure for at least one individual electrical connection comprises at least two portions and at least one gap between the portions for receiving extra bonding material of the bonding layer.

A semiconductor package is provided. The semiconductor package includes a first structure with a first insulating layer and a connection pad which penetrates through the first insulating layer; and a second structure with a second insulating layer bonded to the first insulating layer and a pad structure provided in a recess portion of the second insulating layer. The pad structure is bonded to and wider than the connection pad. The pad structure includes: an electrode pad disposed on a bottom surface of the recess portion; a solder disposed on the electrode pad and bonded to the connection pad; and a conductive support disposed to surround a side surface of the solder on the electrode pad and bonded to the first insulating layer. A melting point of the conductive support is higher than a melting point of the solder.

A semiconductor package and a manufacturing method are provided. The semiconductor package includes a semiconductor die laterally covered by an insulating encapsulation, a first redistribution structure overlying the insulating encapsulation and a back surface of the semiconductor die, a second redistribution structure underlying the insulating encapsulation and an active surface of the semiconductor die opposite to the back surface, active through insulating vias (TIVs) penetrating through the insulating encapsulation, and dummy features. The semiconductor die is electrically coupled to the first redistribution structure through the second redistribution structure and the active TIVs. Each of the dummy features includes a dummy TIV laterally covered by the insulating encapsulation, the dummy TIVs are disposed along package edges in a top view, and the dummy features are electrically floating.

Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a first substrate having first pads on a first surface of the first substrate, a second substrate on the first substrate and having a plurality of second pads on a second surface of the second substrate, and connection terminals between the first substrate and the second substrate and correspondingly coupling the first pad to the second pads. Each of the connection terminals has a first major axis and a first minor axis that are parallel to the first surface of the first substrate and are orthogonal to each other. When viewed in a plan view, the first minor axis of each of the connection terminals is directed toward a center of the first substrate.

Integrated circuit (IC) structures and electronic packages that utilized an inorganic-convertible polymer to improve bond strength and thermal conductivity are described. In one embodiment, the inorganic-convertible polymer acts as a side fill material to seal a die periphery and improve direct bonding strength. In another embodiment, the inorganic-convertible polymer acts as a thermal bonding layer to increase the thermal conductivity between a die and a thermal solution.

A semiconductor package includes a package substrate including first and second interconnection layers sequentially stacked and a first semiconductor device on the package substrate. The first interconnection layer includes first and second lower insulating layers sequentially stacked and a first interconnection line on the second lower insulating layer, the second interconnection layer includes first and second inorganic insulating layers sequentially stacked and a first connection pad in the second inorganic insulating layer, and the first semiconductor device includes a third inorganic insulating layer at a bottom of the first semiconductor device and contacting the second inorganic insulating layer and a second connection pad in the third inorganic insulating layer and contacting the first connection pad. The first and second lower insulating layers are formed of different materials from the first and second inorganic insulating layers, and the first inorganic insulating layer contacts a sidewall and upper surface of the first interconnection line.

A method of forming a semiconductor device is provided. The method include forming an interposer having a first set of conductive connection pads exposed at a first major side of an interposer substrate and a second set of conductive connection pads exposed at a second major side of the interposer substrate. A first semiconductor wafer is mounted on the first major side of the interposer substrate and a second semiconductor wafer is mounted on the second major side of the interposer substrate. A sandwich-like structure is formed by the first semiconductor wafer, interposer, and second semiconductor wafer. The sandwich-like structure is singulated to form a plurality of individual semiconductor device units. A plurality of sidewall connection pads are exposed along an outer perimeter of the interposer.

A semiconductor device is provided. The semiconductor device comprises a semiconductor die comprising a semiconductor substrate and a plurality of transistors arranged at a front side of the semiconductor substrate. Further, the semiconductor die comprises a first electrically conductive structure extending from the front side of the semiconductor substrate to a backside of the semiconductor substrate and a second electrically conductive structure extending from the front side of the semiconductor substrate to the backside of the semiconductor substrate. The semiconductor device further comprises an interposer directly attached to the backside of the semiconductor substrate. The interposer comprises a first trace electrically connected to the first electrically conductive structure of the semiconductor die. Further the interposer comprises the first trace or a second trace electrically connected to the second electrically conductive structure of the semiconductor die.

A semiconductor device includes a lower substrate, a semiconductor element mounted on an upper surface of the lower substrate, an upper substrate disposed on an upper surface of the semiconductor element, one or more through holes extending through the upper substrate in a thickness-wise direction, an encapsulation resin disposed between the lower substrate and the upper substrate and encapsulating the semiconductor element, a wiring layer disposed on an upper surface of the upper substrate, and a covering resin covering the upper surface of the upper substrate and filling the through holes.