A semiconductor device includes a semiconductor fin, an epitaxial region located on a side of the semiconductor fin, a silicide layer disposed on the epitaxial region, a contact plug disposed on the silicide layer and over the epitaxial region, and a self-aligned contact (SAC) layer disposed on the semiconductor fin. At least a part of the SAC layer is implanted with at least one implantation element. The semiconductor fin is spaced apart from the contact plug by the SAC layer.

This disclosure is directed to an interconnect structure of a semiconductor device and a method of forming the interconnect structure. The interconnect structure includes a first metal line, a second metal line on the first metal line, and a conductive via electrically coupling the first and second metal lines. The conductive via includes a protrusion laterally and vertically extending into the first metal line to reduce a contact resistance between the conductive via and the first metal line. The method includes forming the first metal line and a dielectric layer on the first metal line, forming an opening in the dielectric layer to expose the first metal line, and laterally recessing the first metal line in the opening. The method further includes depositing a conductive material in the opening to form the conductive via and the second metal line.

A method is provided for manufacturing a semiconductor structure. The method includes providing a through hole penetrating a stacked layer and exposing a surface of an interconnecting conductive layer; forming a side wall material layer covering at least a side wall and a bottom of the through hole; forming a protective material layer covering the side wall material layer; performing thermal processing on the protective material layer, to cause the protective material layer to implement a material phase change process; etching and removing materials located at the bottom of the through hole to expose the surface of the interconnecting conductive layer, covering the side wall of the through hole, of the side wall material layer as a side wall layer, and taking a remaining protective material layer covering the side wall layer as a protective layer. Working performance of the semiconductor structure is improved.

A semiconductor device includes a semiconductor fin, a gate structure, a capacitor structure, a conductive contact, a hard mask layer, and a pair of spacers. The gate structure is disposed across the semiconductor fin. The capacitor structure is disposed on and in physical contact with the gate structure. The conductive contact is disposed on and in physical contact with the capacitor structure. The conductive contact is a single-layered structure. The hard mask layer laterally surrounds the conductive contact. The spacers laterally surround the gate structure and the hard mask layer. A top surface of the hard mask layer is levelled with top surfaces of the spacers, and the conductive contact extends from below the top surfaces of the spacers to above the top surfaces of the spacers.

Dual-damascene fully-aligned via interconnects with divot fill are provided. In one aspect, an interconnect structure includes: a first interlayer dielectric disposed on a wafer; a metal line(s) embedded in the first interlayer dielectric, where a top surface of the metal line(s) is recessed below a top surface of the first interlayer dielectric; a second interlayer dielectric disposed on the first interlayer dielectric; a conductive via(s) embedded in the second interlayer dielectric and aligned with the metal line(s); a barrier layer along a bottom and a first portion of a sidewall of the metal line(s); and a protective dielectric layer along a second portion of the sidewall of the metal line(s), where the barrier layer and the protective dielectric layer fully separate the metal line(s) from the first interlayer dielectric. A metal cap can be disposed on the metal line(s). A method of fabricating an interconnect structure is also provided.

A method includes depositing an inter-metal dielectric (IMD) layer over a conductive line. A via opening is formed in the IMD layer and directly over the conductive line. A width of the conductive line is greater than a width of the via opening. An overlay measurement is performed. The overlay measurement includes obtaining a backscattered electron image of the via opening and the conductive line and determining an overlay between the via opening and the conductive line according to the backscattered electron image.

A method of forming fully aligned vias in a semiconductor device, the method including forming a first level interconnect line embedded in a first interlevel dielectric (ILD), selectively depositing a dielectric on the first interlevel dielectric, laterally etching the selectively deposited dielectric, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.

A connection structure for an integrated circuit includes: a 1.sup.st layer including a 1.sup.st metal line; a 2.sup.nd layer, above the 1.sup.st layer, including a 1.sup.st via; and a 3.sup.rd layer, above the 2.sup.nd layer, including a 2.sup.nd metal line connected to the 1.sup.st metal line through the 1.sup.st via, wherein the 1.sup.st via comprises a spacer structure at a side of an upper portion of the 1.sup.st via, the spacer structure comprising an insulation material.

A method for manufacturing an interconnect structure includes: forming a first dielectric layer; forming a mask; patterning the first dielectric layer through the mask to form a trench, an inner surface of the trench having two first portions opposite to each other along an X direction, two second portions opposite to each other along a Y direction, and a bottom portion; forming a second dielectric layer over the mask and the patterned first dielectric layer, and along an inner surface of the trench; etching the second dielectric layer by directing an etchant in a predetermined direction such that a first part of the second dielectric layer on the two first portions and the bottom portion is removed, and a second part of the second dielectric layer on the second portions of the trench remains and is formed into two reinforcing spacers; and forming a trench-filling element.

A system and a method for a contact structure are disclosed. The contact structure includes at least a first contact pillar and a second contact pillar. The first contact pillar is connected to a first contact point on a first metal layer in a first semiconductor region at a first depth. The second contact pillar is connected to a second contact point on a second metal layer in the first semiconductor region at a second depth longer than the first depth with respect to a top surface of a second semiconductire region on top of the first semiconductor region. The first and second contact points are isolated in a direction along the first and second depths. The first and second metal layers correspond to first and second wordlines (WLs), respectively, of a memory circuit.