A slurry containing: abrasive grains; a compound X; and water, in which the abrasive grains contain cerium oxide, and a hydrogen bond term dH in Hansen solubility parameters of the compound X is 15.0 MPa.sup.1/2 or more. A polishing method including polishing a surface to be polished by using this slurry.

A method of manufacturing a three-dimensional system-on-chip, comprising providing a memory wafer structure with a first redistribution layer; disposing a first conductive structure and a core die structure and an input/output die structure with a second conductive structure on the first redistribution layer, the input/output die structure being disposed around the core die structure; forming a dielectric layer covering the core die structure, the input/output die structure, and the first conductive structure; removing a part of the dielectric layer and thinning the core die structure and a plurality of input/output die structures to expose the first and second conductive structures; forming a third redistribution layer on the dielectric layer, the third redistribution layer being electrically connected to the first and second conductive structures; forming a plurality of solder balls on the third redistribution layer; performing die saw. A three-dimensional system-on-chip is further provided.

A method of manufacturing a semiconductor device includes performing chemical mechanical polishing on a surface using a polishing slurry including abrasives, and first cleaning by supplying a cleaning slurry including soft particles and a dispersion medium to remove the abrasives from a polished surface on which the chemical mechanical polishing is performed he soft particles having a lower hardness than the polished surface, wherein a zeta potential of one of the soft particles and the abrasives at a pH of the cleaning slurry is greater than 0, and a zeta potential of the other of the soft particles and the abrasives at the pH of the cleaning slurry is less than 0.

Methods of forming a slurry and methods of performing a chemical mechanical polishing (CMP) process utilized in manufacturing semiconductor devices, as described herein, may be performed on semiconductor devices including integrated contact structures with ruthenium (Ru) plug contacts down to a semiconductor substrate. The slurry may be formed by mixing a first abrasive, a second abrasive, and a reactant with a solvent. The first abrasive may include a first particulate including titanium dioxide (TiO.sub.2) particles and the second abrasive may include a second particulate that is different from the first particulate. The slurry may be used in a CMP process for removing ruthenium (Ru) materials and dielectric materials from a surface of a workpiece resulting in better WiD loading and planarization of the surface for a flat profile.

Monitoring operations of a polishing system includes obtaining a time-based sequence of reference images of a component of the polishing system performing operations during a test operation of the polishing system, receiving from a camera a time-based sequence of monitoring images of an equivalent component of an equivalent polishing system performing operations during polishing of a substrate, determining a difference value for the time-based sequence of monitoring images by comparing the time-based sequence of reference images to the time-based sequence of monitoring image using an image processing algorithm, determining whether the difference value exceeds a threshold, and in response to determining the difference value exceeds the threshold, indicating an excursion.

A semiconductor device structure is provided. The semiconductor device structure includes an isolation feature formed over a substrate that includes a first fin and a second fin separated from each other by the isolation feature. The semiconductor device structure also includes an insulating fin structure formed in the isolation feature between the first fin and the second fin. The insulating fin structure includes a first insulating fin base partially formed within the isolation feature and a first insulating capping layer formed over a top surface of the first insulating fin base.

A manufacturing method of a chip-attached substrate includes preparing a stacked substrate including multiple chips, a first substrate to which the multiple chips are temporarily bonded, and a second substrate bonded to the first substrate with the multiple chips therebetween; and separating the multiple chips bonded to the first substrate and the second substrate from the first substrate to bond the multiple chips to one surface of a third substrate including a device layer.

A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.

A semiconductor memory device includes a first region where a plurality of conductive layers, a plurality of insulating layers, a semiconductor layer, and a gate insulating layer are formed and a second region different from the first region above a substrate. The plurality of conductive layers include a plurality of first conductive layers and a plurality of second conductive layers. The semiconductor memory device includes a plurality of first films different from the first conductive layers disposed in same layers as the plurality of first conductive layers in the second region and a plurality of second films different from the second conductive layers and the first films disposed in same layers as the plurality of second conductive layers in the second region.

A semiconductor device includes a gate structure on a substrate, an offset spacer adjacent to the gate structure, a main spacer around the offset spacer, a source/drain region adjacent to two sides of the main spacer, a contact etch stop layer (CESL) adjacent to the main spacer, and an interlayer dielectric (ILD) layer around the CESL. Preferably, a dielectric constant of the offset spacer is higher than a dielectric constant of the main spacer.