A method for manufacturing a semiconductor device includes forming an insulating film on a substrate; forming a recess portion extending toward the substrate from an upper surface of the insulating film; forming a first film on the upper surface of the insulating film and along an inner surface of the recess portion, wherein the first film has hydrophobicity; treating an upper surface of the first film to be hydrophilic; and polishing the first film until the upper surface of the insulating film is exposed.

A semiconductor device includes a bottom electrode structure disposed over a semiconductor substrate. The bottom electrode structure includes a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer, arranged from bottom to top. The first metal layer, the third metal layer and the fifth metal layer include a first metal material, and the second metal layer and the fourth metal layer include a second metal material different from the first metal material. The semiconductor device also includes a high-k dielectric structure disposed on opposite sidewalls of the bottom electrode structure. The opposite sidewalls of the bottom electrode structure are step-shaped. The semiconductor device further includes a top electrode structure laterally surrounding the bottom electrode structure and separated from the bottom electrode structure by the high-k dielectric structure.

A method for forming a semiconductor device includes followings. A metal layer is formed to embedded in a first dielectric layer. An etch stop layer is formed over the metal layer and the first dielectric layer. A second dielectric layer is formed over the etch stop layer. A portion of the second dielectric layer is removed to expose a portion of the etch stop layer and to form a via by a dry etching process. The portion of the etch stop layer exposed by the second dielectric layer is removed to expose the metal layer and to form a damascene cavity by a wet etching process. A damascene structure is formed in the damascene cavity.

A method of manufacturing a semiconductor device includes forming a dielectric layer conformally over a plurality of fins on a substrate, forming a first high-k layer conformally over the dielectric layer, and forming a flowable oxide over the first high-k layer. Forming the flowable oxide includes filling first trenches adjacent fins of the plurality of fins. The method further includes recessing the flowable oxide to form second trenches between adjacent fins of the plurality of fins, forming a second high-k layer over the first high-k layer and the flowable oxide, performing a planarization that exposes top surfaces of the plurality of fins, and recessing the dielectric layer to form a plurality of dummy fins that include remaining portions of the first and second high-k layers and the flowable oxide.

The present disclosure relates to chemical mechanical polishing (CMP) compositions for polishing an amorphous carbon (C) film, i.e., a hardmask. In particular, the CMP compositions include a silica abrasive, an anionic surfactant, an aluminum salt and water, combined in specified amounts to provide a composition with advantageous properties such as high C removal rate while also maintaining a low silicon removal rate.

A method for manufacturing an electrical interconnection structure including a step of providing an initial structure including a substrate, an electrically conductive lower element, a cavity formed in the substrate and having an inner wall internally defining an access to the lower element, and an electrically insulating layer; a step of forming an interconnection element in the cavity; and a final polishing step, wherein a portion of the interconnection element and at least one part of the electrically insulating layer are removed simultaneously by chemical-mechanical polishing using a final polishing agent, thereby forming the electrical interconnection structure.

A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.

Provided is a polishing composition that can polish a carbon film at a high polishing removal rate, and can polish the carbon film at a high polishing removal rate with respect to a polishing removal rate of a silicon nitride film. A polishing composition, containing an anion-modified silica particle; a nonionic surfactant; and an anionic polymer, wherein a pH of the polishing composition is 1.0 or more and 5.0 or less.

Provided is a polishing composition that can polish a carbon film at a high polishing removal rate. A polishing composition containing abrasive grains and a nonionic surfactant, wherein the polishing composition is used for polishing an object to be polished containing a carbon film.

A chemical mechanical polishing composition comprises, consists of, or consists essentially of a liquid carrier and ceria polymer composite particles dispersed in the liquid carrier. The ceria polymer composite particles comprise, consist of, or consist essentially of ceria particles covalently bonded to and at least partially embedded in a polymer matrix.