A method for automatically generating chip identifier for semiconductor dies in a stacked structure is provided. The method includes the following steps: obtaining a first semiconductor die and a second semiconductor die, wherein the first semiconductor die and the second semiconductor die include a first identifier generation circuit and a second identifier generation circuit, respectively; forming a stacked structure by stacking the second semiconductor die on the first semiconductor die, wherein the first identifier generation circuit is electrically connected to the second identifier generation circuit; and generating a first chip identifier and a second chip identifier for the first semiconductor die and the second semiconductor die by the first identifier generation circuit and the second identifier generation circuit, respectively. The second chip identifier is generated using the first chip identifier and an auxiliary input signal.

A semiconductor die assembly is introduced in this disclosure. The semiconductor die assembly includes one or more semiconductor dies, a dielectric layer disposed under a bottom surface of the one or more semiconductor dies, and metal fragments or a metal layer disposed under the dielectric layer, wherein metal-OH bonds or metal-OSiOH bonds are disposed on a bottom surface of the dielectric layer. Alternatively, the semiconductor die assembly includes one or more semiconductor dies, a metal layer disposed under a bottom surface of the one or more semiconductor dies, and a metal oxidation layer disposed under the dielectric layer, wherein the metal oxidation layer comprises metal-OH bonds or metal-OSiOH bonds.

Semiconductor devices having integrated cooling systems, and associated systems and methods, are disclosed herein. An example of a semiconductor device according to the present technology is a system-in-package device that includes a base substrate, a processing device and a high-bandwidth memory device that are each integrated with the base substrate, and a package cooling device that is thermally coupled to the processing device and the high-bandwidth memory device. In some embodiments, the package cooling device includes a first heat spreader thermally coupled to an upper surface of the processing device, a second heat spreader thermally coupled to an upper surface of the high-bandwidth memory device, a thermoelectric cooling device positioned between and thermally coupled to a portion of the first heat spreader and the second heat spreader, and a heat exchanger thermally coupled to the first heat spreader.

Provided is a semiconductor package including a first redistribution structure, a second redistribution structure on the first redistribution structure, a first semiconductor device being between the first redistribution structure and the second redistribution structure, a first dummy chip being apart from the first semiconductor device in a lateral direction, a first connection wire being between the first semiconductor device and a first side surface of the first dummy chip, the first connection wire electrically connecting the first redistribution structure to the second redistribution structure, and a second connection wire being on a second side surface opposite to the first side surface of the first dummy chip, the second connection wire electrically connecting the first redistribution structure to the second redistribution structure.

A stacked semiconductor device comprising a plurality of fin capacitors disposed in or on a semiconductor substrate is described. The plurality of fin capacitors is arranged to form a fin capacitor array. A fin capacitor included in the plurality of fin capacitors comprising a first electrode, a second electrode, and an insulating material. The first electrode includes a first planar portion and a plurality of first fins extending from the first planar portion. The second electrode includes a second planar portion and a plurality of second fins extending from the second planar portion. The plurality of first fins is nested with the plurality of second fins such that the plurality of first fins and the plurality of second fins are both disposed between the first planar portion and the second planar portion. The insulating material is disposed between the plurality of first fins and the plurality of second fins.

An isotope battery may include a plurality of isotope battery sheets that are stacked in a first direction, a first external electrode, and a second external electrode. Each isotope battery sheet of the plurality of isotope battery sheets includes: a substrate including a semiconductor material; and a radiation source. The radiation source may extend through at least a portion of the substrate in the first direction. The substrate includes a first region having a first conductive type and a second region having a second conductive type. The first region may be between the radiation source and the second region. The first external electrode and the second external electrode are configured to transfer electrical energy generated by the plurality of stacked isotope battery sheets to an external load. The isotope battery has the effect of generating electrical energy with a high energy density.

A stacked semiconductor device includes a base semiconductor die and a plurality of core semiconductor dies that are stacked in a vertical direction, a plurality of temperature sensing circuits included in the plurality of core semiconductor dies, respectively, a conversion circuit included in the base semiconductor die, and a plurality of vertical conductive paths electrically connecting the base semiconductor die and the plurality of core semiconductor dies, through silicon vias provided in the plurality of vertical conductive paths in the vertical direction. The plurality of temperature sensing circuits generate sensing voltages that vary according to operating temperatures, and transfer the sensing voltages to the conversion circuit through a first vertical conductive path among the plurality of vertical conductive paths. The conversion circuit converts the sensing voltages into a temperature code.

A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias include a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of through-vias not coupled to I/O circuitry on the semiconductor die. The plurality of semiconductor dies are stacked such that the first group of through-vias in a first one of the plurality of semiconductor dies are aligned with respective ones of at least a portion of the second group of through-vias in a second one of the plurality of semiconductor dies.

A semiconductor package including a package substrate defining a cavity therein; a first semiconductor chip on the package substrate; a first bump between the package substrate and the first semiconductor chip, the first bump electrically connecting the package substrate and the first semiconductor chip; a second semiconductor chip on the package substrate, the second semiconductor chip being at least partially in the cavity; a first bonding wire electrically connecting the package substrate and the second semiconductor chip; and an underfill layer covering the first bump and at least a portion of the first bonding wire.

A semiconductor device includes a capacitor on a first substrate, a channel on the capacitor, a gate electrode at least partially overlapping the channel in a horizontal direction, a bit line structure on the gate electrode and the channel, a first wiring structure on the bit line structure, a bonding pad structure on the first wiring structure, a second wiring structure on the bonding pad structure, a second substrate on the second wiring structure, a transistor beneath the second substrate, a third wiring structure on the second substrate, an isolation pattern extending through the second substrate, and a through via extending through the isolation pattern.