A semiconductor package includes a first package having a first semiconductor chip, a second semiconductor chip and a core member including a through-hole. At least one of the first and second semiconductor chips is disposed in the through-hole. An encapsulant is disposed in the through-hole. A first redistribution layer is disposed above the core member and is electrically connected to the first and second semiconductor chips. A second redistribution layer is disposed under the core member and electrically connects the first and second semiconductor chips with an external PCB. Core vias penetrate the core member and electrically connect the first and second redistribution layers. A second package is disposed on the first package and includes a third semiconductor chip. A plurality of first electrical connection structures electrically connects the first and second packages. A plurality of second electrical connection structures electrically connects the semiconductor package with the external PCB.

A microelectronic device package includes: a package substrate having a first set of leads spaced from a first die pad configured for mounting semiconductor devices, and a second set of leads spaced from a second die pad configured for mounting additional semiconductor devices, the first die pad and the first set of leads spaced from the second die pad and the second set of leads. Semiconductor devices are mounted to the first die pad and second die pad. A ceramic interposer is mounted to the package substrate in thermal contact with at least the first die pad. Mold compound covers the semiconductor devices, a portion of the ceramic interposer, and portions of the first set and the second set of leads.

A semiconductor package includes a first substrate including a first interconnection structure, a first semiconductor chip, a second semiconductor chip, a second substrate, a molding layer between the first substrate and the second substrate, a plurality of conductive bumps that electrically connect the first interconnection structure to a first chip pad on a second surface of the first semiconductor chip that is opposite to the first surface of the first semiconductor chip, and a plurality of conductive wires that electrically connect the first interconnection structure to a second chip pad on a second surface of the second semiconductor chip that is opposite to the first surface of the second semiconductor chip.

A semiconductor device assembly includes a plurality of stacks of semiconductor devices horizontally spaced apart by a gap fill material, each including multiple devices coupled by TSVs to external package contacts through an RDL, and a device connection layer formed over the stacks and including a first plurality of contacts coupled to the TSVs, a second plurality of contacts facing away from the TSVs, a first plurality of conductors coupling contacts of the first plurality to corresponding contacts of the second plurality, and a second plurality of conductors coupling contacts of the second plurality to other contacts of the second plurality. The assembly further includes a multi-reticle semiconductor device over the device connection layer and including a plurality of circuit regions horizontally spaced apart from one another by a reticle-edge region absent any electrical conductors. The second plurality of conductors in the device connection layer operably interconnect the circuit regions.

A package structure includes a circuit substrate, a semiconductor package, a first ring structure and a second ring structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The first ring structure is attached to the circuit substrate and surrounding the semiconductor package, wherein the first ring structure includes a central opening and a plurality of corner openings extending out from corners of the central opening, the semiconductor package is located in the central opening, and the plurality of corner openings is surrounding corners of the semiconductor package.

A technical idea of a present invention provides a method for manufacturing a semiconductor package, comprising: a step of disposing a plurality of dies on a carrier while being spaced apart from each other in a horizontal direction; a first sawing step of sawing the carrier to separate the carrier into a plurality of sub-panels on which the plurality of dies are disposed; a step of testing the dies; and a second sawing step of sawing between each of the dies of the sub-panels to separate the sub-panels into individual semiconductor packages; wherein the carrier includes a plurality of first regions in which the dies are disposed and a second region in which the dies are not disposed, and wherein a first horizontal distance from a side of the carrier to the first region is smaller than a second horizontal distance from the first region to the first region.

Embodiments relate to an electronic circuit implemented using a first integrated circuit die, a second integrated circuit die, and an interposer connecting the first integrated circuit die to the second integrated circuit die. The first integrated circuit die implements a first electronic circuit. The first integrated circuit die includes a first set of contacts on a bottom surface, a buried power rail (BPR), and a plurality of through-silicon vias (TSV) for connecting the BPR to the first set of contacts. The interposer includes a second set of contacts and a power delivery network (PDN). Each contact of the second set of contact corresponds to a contact of the first set of contacts of the first integrated circuit die. The PDN is configured to route a power supply voltage to the second set of contacts.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface with first conductive contacts and an opposing second surface with second conductive contacts, in a first layer; a die attach film (DAF), at the first surface of the first die, including through-DAF vias (TDVs), wherein respective ones of the TDVs are electrically coupled to respective ones of the first conductive contacts; a conductive pillar in the first layer; and a second die, in a second layer on the first layer, wherein the second die is electrically coupled to the second conductive contacts on the second surface of the first die and electrically coupled to the conductive pillar.

A semiconductor package includes a plurality of first semiconductor dies, a plurality of first bonding pads, a bridge layer, a plurality of second bonding pads and a plurality of second semiconductor dies. The first bonding pads are disposed on the first semiconductor dies. The bridge layer is disposed on the first bonding pads, wherein the bridge layer is electrically connected to the first semiconductor dies through the first bonding pads. The second bonding pads are disposed on the bridge layer, wherein the second bonding pads are electrically connected to the first bonding pads through the bridge layer. The second semiconductor dies are disposed on and electrically connected to the second bonding pads, wherein an active surface of the first semiconductor dies is facing an active surface of the second semiconductor dies.

Disclosed is a semiconductor package structure, which includes a first substrate, a second substrate, a processor module, a chip stack structure, and a signal adapter board. The processor module is arranged on a first plane of the first substrate and connected to the first substrate; the chip stack structure is arranged on the first plane of the first substrate and connected to the first substrate, and the first substrate is configured to transmit a first-type signal between the processor module and the chip stack structure; the signal adapter board is connected to the processor module and the chip stack structure, and is configured to transmit a second-type signal between the processor module and the chip stack structure; and the second substrate is arranged parallel to the first substrate and connected to a second plane of the first substrate, and the second plane of the first substrate is parallel to and opposite to the first plane of the first substrate.