A semiconductor module includes a first semiconductor chip including a first surface and a second surface parallel to a first direction and a second direction, a sub-semiconductor cube including a second semiconductor chip and a logic chip electrically connected to the second semiconductor chip stacked in the first direction, and a semiconductor cube arranged on the second surface, wherein the logic chip includes a plurality of first inductors arranged parallel to a third direction perpendicular to the first direction and the second direction, the first semiconductor chip includes a plurality of routers and a plurality of second inductors arranged parallel to the second surface, a plurality of circuits in the first semiconductor chip are electrically connected using the plurality of routers, and the logic chip and the first semiconductor chip are configured to be able to communicate contactlessly using the plurality of first inductors and the plurality of second inductors.

A semiconductor module includes a first semiconductor chip including a first surface and a second surface parallel to a first direction and a second direction, a sub-semiconductor cube including a second semiconductor chip and a logic chip electrically connected to the second semiconductor chip stacked in the first direction, and a semiconductor cube arranged on the second surface, wherein the logic chip includes a plurality of first inductors arranged parallel to a third direction perpendicular to the first direction and the second direction, the first semiconductor chip includes a plurality of routers and a plurality of second inductors arranged parallel to the second surface, a plurality of circuits in the first semiconductor chip are electrically connected using the plurality of routers, and the logic chip and the first semiconductor chip are configured to be able to communicate contactlessly using the plurality of first inductors and the plurality of second inductors.

Provided is a semiconductor module including a stacked substrate in which a plurality of wiring layers are stacked, and a plurality of semiconductor devices mounted on a first surface of the stacked substrate, wherein the plurality of wiring layers have a first wiring layer having a high-potential wiring to which a high potential is applied, a second wiring layer having a low-potential wiring to which a low potential is applied, and a third wiring layer having a connection wiring which connects the plurality of semiconductor devices mounted on the first surface of the stacked substrate to each other, and the high-potential wiring and the low-potential wiring are at least partially overlapped with each other in a stack direction.

Provided is a semiconductor module including a stacked substrate in which a plurality of wiring layers are stacked, and a plurality of semiconductor devices mounted on a first surface of the stacked substrate, wherein the plurality of wiring layers have a first wiring layer having a high-potential wiring to which a high potential is applied, a second wiring layer having a low-potential wiring to which a low potential is applied, and a third wiring layer having a connection wiring which connects the plurality of semiconductor devices mounted on the first surface of the stacked substrate to each other, and the high-potential wiring and the low-potential wiring are at least partially overlapped with each other in a stack direction.

A semiconductor device includes: a substrate with a circuit pattern: a semiconductor chip mounted on the circuit pattern and electrically connected to the circuit pattern; a frame member including a wall portion; and a plate-shaped terminal electrically connected to the circuit pattern. The wall portion surrounds the substrate. The terminal includes a first region attached to the wall portion, and a second region continuous to the first region and located inside the frame member. A distance between an inner wall surface of the wall portion and the circuit pattern is 500 m or less. The second region is directly connected to the circuit pattern.

A semiconductor device includes: a substrate with a circuit pattern: a semiconductor chip mounted on the circuit pattern and electrically connected to the circuit pattern; a frame member including a wall portion; and a plate-shaped terminal electrically connected to the circuit pattern. The wall portion surrounds the substrate. The terminal includes a first region attached to the wall portion, and a second region continuous to the first region and located inside the frame member. A distance between an inner wall surface of the wall portion and the circuit pattern is 500 m or less. The second region is directly connected to the circuit pattern.

A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.

A package and a manufacturing method for the package are provided. The package includes a semiconductor die, an insulating encapsulant and a redistribution structure. The redistribution structure comprises a dielectric layer and a stacked via structure embedded in the dielectric layer. The stacked via structure comprises a first via plug, a first diffusion layer including first dopants, a second via plug, and a second diffusion layer including second dopants. The first via plug includes the first dopants dispersed within a first metal material of the first via plug, and the second via plug includes the second dopants dispersed within a second metal material of the second via plug.

An integrated fan-out package includes a redistribution structure, a die, an encapsulant and a conductive bump. The redistribution structure has a first surface and a second surface opposite to the first surface, wherein the redistribution structure comprises an under-bump metallization (UBM) pattern disposed on the first surface. The die is disposed on the second surface of the redistribution structure. The encapsulant encapsulates the die. The conductive bump is disposed on the UBM pattern, wherein the UBM pattern has a configuration surface over the first surface, the conductive bump is located on the configuration surface, and a bottom area of the conductive bump is smaller than an area of configuration surface.

An image display device includes: a light-transmitting substrate including a first surface; a circuit element on the first surface; a first wiring layer located on the circuit element and electrically connected to the circuit element; a first insulating film covering the circuit element and the first wiring layer on the first surface; a first plug located on the first insulating film and electrically connected to the first wiring layer; a first light-emitting element located on the first plug, electrically connected to the first plug, and including a light-emitting surface on a surface at a side opposite to a surface on a first insulating film side; a second insulating film covering at least a portion of the first light-emitting element, the first insulating film, and the first plug; and a second wiring layer located on the second insulating film and electrically connected to the light-emitting surface of the first light-emitting element.