A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip.

An electronic device includes a three-dimensionally non-planar mold body defining at least part of one of a non-planar side surface and an opposed non-planar side surface of the electronic device, an electrically conductive structure provided on one of the non-planar side surface and the opposing non-planar side surface, and at least one electric entity at least partially inside of the three-dimensionally non-planar mold body.

An electronic device includes a three-dimensionally non-planar mold body defining at least part of one of a non-planar side surface and an opposed non-planar side surface of the electronic device, an electrically conductive structure provided on one of the non-planar side surface and the opposing non-planar side surface, and at least one electric entity at least partially inside of the three-dimensionally non-planar mold body.

An example chip packaging structure includes a redistribution layer, and the redistribution layer includes a first copper pillar layer, a second copper pillar layer, and a metal routing layer. The first copper pillar layer includes a plurality of first copper pillars, and the second copper pillar layer includes a plurality of second copper pillars. The metal routing layer is located between the first copper pillar layer and the second copper pillar layer, and the metal routing layer is electrically connected to the plurality of first copper pillars and the plurality of second copper pillars. The plurality of first copper pillars are coplanar on a first side close to the metal routing layer, and the plurality of second copper pillars are coplanar on a second side away from the metal routing layer.

An example chip packaging structure includes a redistribution layer, and the redistribution layer includes a first copper pillar layer, a second copper pillar layer, and a metal routing layer. The first copper pillar layer includes a plurality of first copper pillars, and the second copper pillar layer includes a plurality of second copper pillars. The metal routing layer is located between the first copper pillar layer and the second copper pillar layer, and the metal routing layer is electrically connected to the plurality of first copper pillars and the plurality of second copper pillars. The plurality of first copper pillars are coplanar on a first side close to the metal routing layer, and the plurality of second copper pillars are coplanar on a second side away from the metal routing layer.

A package includes a substrate, and a first die, a second die, a first structural member, and a second structural member that are disposed on the substrate. A first dielectric material is disposed between the first die and the second die. The first structural member is disposed on a side that is of the first die and that is away from the substrate, and the first die is located in a region of orthographic projection of the first structural member on a surface of the substrate. The second structural member is disposed on a side that is of the second die and that is away from the substrate, the second die is located in a region of orthographic projection of the second structural member on the surface of the substrate, and there is a gap between the first structural member and the second structural member.

A package includes a substrate, and a first die, a second die, a first structural member, and a second structural member that are disposed on the substrate. A first dielectric material is disposed between the first die and the second die. The first structural member is disposed on a side that is of the first die and that is away from the substrate, and the first die is located in a region of orthographic projection of the first structural member on a surface of the substrate. The second structural member is disposed on a side that is of the second die and that is away from the substrate, the second die is located in a region of orthographic projection of the second structural member on the surface of the substrate, and there is a gap between the first structural member and the second structural member.

Various aspects relate to mechanisms for coupling a three-dimensional semiconductor cube to a host substrate including a plurality of substrate communication points. The three-dimensional semiconductor cube includes a plurality of cube communication points corresponding to the plurality of substrate communication points and at least one mounting mechanism that couples the three-dimensional semiconductor cube to the host substrate.

A device may include a plurality of chiplets stacked on top of each other. Each chiplet includes a central region and an edge region outside the central region; one or more electronic components disposed within the central region; and a plurality of through-chiplet vias extending through the chiplet. The plurality of through-chiplet vias are disposed in the edge region. The device may further include a coil including a plurality of turns formed in at least two chiplets of the plurality of chiplets. Each turn includes at least two through-chiplet vias of at least one chiplet of the plurality of chiplets. The through-chiplet vias of the plurality of through-chiplet vias of the at least two turns of the plurality of turns of the coil are formed in a common plane perpendicular to main surfaces of the plurality of chiplets.

A device may include a plurality of chiplets stacked on top of each other. Each chiplet includes a central region and an edge region outside the central region; one or more electronic components disposed within the central region; and a plurality of through-chiplet vias extending through the chiplet. The plurality of through-chiplet vias are disposed in the edge region. The device may further include a coil including a plurality of turns formed in at least two chiplets of the plurality of chiplets. Each turn includes at least two through-chiplet vias of at least one chiplet of the plurality of chiplets. The through-chiplet vias of the plurality of through-chiplet vias of the at least two turns of the plurality of turns of the coil are formed in a common plane perpendicular to main surfaces of the plurality of chiplets.