A method of fabricating a semiconductor device includes forming a protective structure on at least one die on a substrate. The protective structure exposes one or more electrical contacts on a first surface of the at least one die. Respective terminals are formed on the one or more electrical contacts exposed by the protective structure. Related packages and fabrication methods are also discussed.

Methods of manufacturing a sealed electrical device for embedded integrated circuit (IC) chips are described, as well as the resulting devices themselves. The sealed electrical device is created by removing material from a substrate to form a pocket in the substrate. An unencapsulated, or bare, IC chip can be placed within the pocket with connection pads of the IC chip facing outward. A gap between the IC chip and a side of the pocket can be filled with a filler. An uncured polymer can be cast over the substrate, which can be allowed to cure into a flat polymer sheet. Conductive traces can be patterned on the polymer sheet and to the connection pads of the IC chip. The conductive traces can then be coated with polymer to form a ribbon cable. Substrate can then be removed from underneath the ribbon cable, leaving substrate around the pocket to protect the IC chip.

A sensor package includes a circuit substrate, a sensor die, an electrical connection, a dielectric dam, a cover layer, and an encapsulant. The circuit substrate includes a first side, a second side opposite to the first side, and a cavity recessed from the first side toward the second side. The sensor die is disposed in the cavity and includes a first side, a sensing area on the first side, and a second side opposite to the first side and facing the circuit substrate. The electrical connection electrically connects the first sides of the sensor die and the circuit substrate. The dielectric dam is disposed on the first side of the circuit substrate and outside the cavity, and the dielectric dam partially covers the electrical connection. The encapsulant is disposed on the first side of the circuit substrate and laterally covers the dielectric dam and the cover layer.

Methods, systems, and devices for hybrid bonding techniques for stacked semiconductor systems are described. A semiconductor device may be formed to include a stack of memory array dies. Each memory array die of the stack may be bonded with at least one other memory array die in the stack. The semiconductor device may include a set of multiple dielectric material portions, with each dielectric material portion extending beyond a lateral boundary of the stack and extending from a respective semiconductor substrate portion of a corresponding memory array die. The semiconductor device may also include a logic die bonded with a first memory array die of the stack, and the logic die may include circuitry operable to facilitate one or more access operations of the memory array dies of the stack.

A semiconductor package includes a package substrate, a chip stack having first semiconductor chips stacked on the package substrate, a first molding film covering the chip stack on the package substrate, a first connection wire vertically penetrating the first molding film to be connected to the package substrate, and exposed onto an upper surface of the first molding film, a second semiconductor chip disposed on the first molding film, and having a first chip pad disposed on one surface facing the package substrate, a second molding film covering the second semiconductor chip on the first molding film, and a connection terminal connecting the first chip pad and an upper end of the first connection wire.

A semiconductor device package assembly is introduced in this disclosure. The semiconductor device assembly includes a plurality of semiconductor device packages, each one of the plurality of semiconductor device packages including a package substrate having top and bottom surfaces, one or more semiconductor dice disposed on the top surface of the package substrate, and a plurality of contact pads disposed on a bottom surface of the package substrate. The semiconductor device assembly also includes a redistribution layer (RDL) on which the plurality of semiconductor device packages are disposed, and a plurality of solder balls disposed on an RDL surface opposite where the plurality of semiconductor device packages are disposed, wherein the RDL electrically connects a first semiconductor device package and a second semiconductor device package of the plurality of semiconductor device packages to one or more of the plurality of solder balls.

An optical engine device includes an electronic integrated circuit (EIC) chip, and a photonic chip on the EIC chip, where the PIC chip includes a first photonic chip sidewall, a photonic chip substrate having an inclined upper surface, and a reflective pattern on the inclined upper surface of the photonic chip substrate, and where at least a portion of the reflective pattern is horizontally spaced apart from the first photonic chip sidewall.

A semiconductor package includes a lower interconnect structure. The lower interconnect structure includes a lower insulating layer and lower interconnect patterns. A first encapsulation layer is disposed on the lower interconnect structure. A pillar electrode penetrating the first encapsulation layer and connected to the lower interconnect patterns is provided. An upper interconnect structure disposed within the first encapsulation layer and having an upper insulating layer and upper interconnect patterns is provided. A distance between an upper surface of the lower interconnect structure and an uppermost end of the first encapsulation layer is larger than a distance between the upper surface of the lower interconnect structure and an uppermost end of the upper interconnect structure. A second encapsulation layer is disposed on the first encapsulation layer. A semiconductor chip disposed within the second encapsulation layer and connected to the pillar electrode and upper interconnect patterns is provided.

A semiconductor package contains a first semiconductor die, electrically coupled to a plurality of leads around a perimeter of the semiconductor package via a molded interconnect. The molded interconnect comprises a plurality of embedded interconnects in a first mold compound which electrically couple the plurality of bond pads of the first semiconductor die to the plurality of leads of the semiconductor package. The molded interconnect may have a greater cross-sectional area at a given pitch compared to a similar wire bonded semiconductor package and allow advantageous thermal management of the semiconductor package compared to other electrical coupling techniques. The molded interconnect may allow small high-power integrated circuits to be packaged with a package footprint which is smaller than would otherwise be available.

A semiconductor die stack includes a first semiconductor die having a first lattice direction, and a second semiconductor die bonded to the first semiconductor die and having a second lattice direction different than the first lattice direction.