A package comprising a first substrate, a first integrated device coupled to the first substrate, a second substrate coupled to the first substrate through a first plurality of solder interconnects such that the first integrated device is located between the first substrate and the second substrate, wherein the second substrate includes a first surface and a second surface, an electrical device coupled to a second surface of the second substrate such that the electrical device is located between the first substrate and the second substrate, and an encapsulation layer coupled to the first substrate and the second substrate. The encapsulation layer is located between the first substrate and the second substrate. The encapsulation layer encapsulates the first integrated device and the electrical device.

A semiconductor device is provided, which includes a semiconductor die and a redistribution layer. The redistribution layer is formed on the semiconductor die, and includes a plurality of center pads, a plurality of edge pads, and a plurality of conductive wires electrically connecting the plurality of center pads to the plurality of edge pads. Each of the plurality of conductive wires comprises at least two turning points, and an inner angle at each turning point is greater than a predetermined angle.

A package structure is provided. The package structure includes a processing module, a storage module, and a power regulating module. The processing module includes a processing element having a first side configured to receive power. The power regulating module is disposed adjacent to the processing module. The power regulating module includes a first portion and a second portion. The first portion is configured to decouple a first noise from a first power signal and transmit the first power signal to the first side of the processing element. The second portion is configured to transmit a second power signal to the storage module.

Conductive vias for 3D integration may be formed during or after assembly to couple dies or die stacks. In one example, such conductive vias may extend through the dies or die stacks and through an interface with conductive bumps, without terminating on the bumps. Bypassing conductive bumps with a conductive via may enable improved performance, power delivery, and thermal management. In one example, an assembly includes a first IC structure (such as a substrate, interposer, or other IC structure) and a second IC structure (such as a die or die stack) over the first IC structure. The assembly includes an interface layer between the first IC structure and the second IC structure, where the interface layer includes a plurality of conductive bumps. A conductive via extends through the interface layer with the bumps and is coupled with a conductive element of the first IC structure.

Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a first substrate having first pads on a first surface of the first substrate, a second substrate on the first substrate and having a plurality of second pads on a second surface of the second substrate, and connection terminals between the first substrate and the second substrate and correspondingly coupling the first pad to the second pads. Each of the connection terminals has a first major axis and a first minor axis that are parallel to the first surface of the first substrate and are orthogonal to each other. When viewed in a plan view, the first minor axis of each of the connection terminals is directed toward a center of the first substrate.

A metal bump containing structure is provided which has a substantially flat top surface and enhanced coplanarity with other like metal bump containing structures. The metal bump containing structures include a metal bump having a curved top surface, and a first metal liner located along an outermost sidewall and present at least partially on the curved top surface of the metal bump.

In one example, an electronic device comprises a substrate having a first conductive structure, an electronic component coupled to the first conductive structure at a first side of the substrate, wherein the electronic component includes a first side facing the first side of the substrate and a second side opposite the first side, vertical interconnects around the electronic component, wherein the vertical interconnects are coupled to the first conductive structure at the first side of the substrate, an interposer having a second conductive structure coupled to the plurality of vertical interconnects, a thermal body coupled between the electronic component and the interposer, and an encapsulant between the substrate and the interposer, around the thermal body, around the plurality of vertical interconnects, and around the electronic component. Other examples and related methods are also disclosed herein.

A package structure includes a circuit substrate, a semiconductor package, a first ring structure and a second ring structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The first ring structure is attached to the circuit substrate and surrounding the semiconductor package, wherein the first ring structure includes a central opening and a plurality of corner openings extending out from corners of the central opening, the semiconductor package is located in the central opening, and the plurality of corner openings is surrounding corners of the semiconductor package.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface with first conductive contacts and an opposing second surface with second conductive contacts, in a first layer; a die attach film (DAF), at the first surface of the first die, including through-DAF vias (TDVs), wherein respective ones of the TDVs are electrically coupled to respective ones of the first conductive contacts; a conductive pillar in the first layer; and a second die, in a second layer on the first layer, wherein the second die is electrically coupled to the second conductive contacts on the second surface of the first die and electrically coupled to the conductive pillar.

A stacked package structure and a forming method thereof are disclosed. The forming method includes mounting a first active surface of a first chip facing down on an upper surface of a substrate; forming a chip stacking structure on a first back surface of the first chip, including a plurality of second chips stacked sequentially in a vertical direction; performing a mass reflow process to solder the micro bumps of the upper second chip to the second connection terminals of the adjacent lower second chip; and performing a molded underfill process to form a molding layer filled between the upper and lower second chips and between the lower second chip and the first chip. This improves packaging efficiency, prevents the micro bumps from collapsing, and ensures evenness during stacking.