A microelectronic device includes a die with input/output (I/O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically conductive pillars which are electrically coupled to the I/O terminals, and extend through the dielectric layer to an exterior of the microelectronic device. Each pillar includes a column electrically coupled to one of the I/O terminals, and a head contacting the column at an opposite end of the column from the I/O terminal. The head extends laterally past the column in at least one lateral direction. Methods of forming the pillars and the dielectric layer are disclosed.

A semiconductor package including a package redistribution layer, a cover insulating layer on the package redistribution layer; a lower semiconductor chip arranged between the package redistribution layer and the cover insulating layer and electrically connected to the package redistribution layer, a lower molding layer surrounding the lower semiconductor chip and filling between the package redistribution layer and the cover insulating layer, a plurality of connection posts electrically connected to the package redistribution layer by passing through the cover insulating layer and the lower molding layer, an upper semiconductor chip arranged above the cover insulating layer electrically connected to the plurality of connection posts, and an upper molding layer filling between the upper semiconductor chip and the cover insulating layer and surrounding the upper semiconductor chip may be provided.

A semiconductor package includes a package substrate, a first semiconductor chip mounted on the package substrate and that includes a first semiconductor substrate that includes through electrodes, and a second semiconductor chip disposed on the first semiconductor chip and that includes a second semiconductor substrate that includes an active surface and an inactive surface. The second semiconductor chip further includes a plurality of isolated heat dissipation fins that extend in a vertical direction from the inactive surface.

Disclosed are techniques for integrated circuits (ICs). In an aspect, an IC package includes a package substrate having an upper surface, a lower surface, a first side, and a second side perpendicular to the first side. The package substrate includes a metallization structure. The IC package further includes an IC die attached to the upper surface of the package substrate; first package bumps on the lower surface of the package substrate; and second package bumps on the lower surface of the package substrate. The first package bumps are arranged adjacent to one another along a diagonal direction that is diagonal to the package substrate, and the second package bumps are arranged adjacent to one another along the diagonal direction.

A semiconductor package and a manufacturing method thereof are described. The semiconductor package includes a package having dies encapsulated by an encapsulant, a redistribution circuit structure, first and second modules and affixing blocks. The redistribution circuit structure is disposed on the package. The first and second modules are disposed on and respectively electrically connected to the redistribution circuit structure by first and second connectors disposed there-between. The first and second modules are adjacent to each other and disposed side by side on the redistribution circuit structure. The affixing blocks are disposed on the redistribution circuit structure and between the first and second modules and the redistribution circuit structure. The affixing blocks include first footing portions located below the first module, second footing portions located below the second module, and exposed portions exposed from the first and second modules. The affixing blocks join the first and second modules to the redistribution circuit structure.

Microelectronic die package structures formed according to some embodiments may include a substrate and a die having a first side and a second side. The first side of the die is coupled to the substrate, and a die backside layer is on the second side of the die. The die backside layer includes a plurality of unfilled grooves in the die backside layer. Each of the unfilled grooves has an opening at a surface of the die backside layer, opposite the second side of the die, and extends at least partially through the die backside layer.

A three-dimensional integrated circuit structure including: a first die including a first power delivery network, a first substrate, a first device layer, and a first metal layer; a second die on the first die, the second die including a second power delivery network, a second substrate, a second device layer, and a second metal layer; a first through electrode extending from the first power delivery network to a top surface of the first metal layer; and a first bump on the first through electrode, the second power delivery network including: lower lines to transfer power to the second device layer; and a pad connected to a lowermost one of the lower lines, the first bump is interposed between and connects the first through electrode and the pad, and the first power delivery network is connected to the second power delivery network through the first bump and the first through electrode.

In a described example, an apparatus includes a transistor formed on a semiconductor substrate, the transistor including: a transistor gate and an extended drain between the transistor gate and a transistor drain contact; a transistor source contact coupled to a source contact probe pad; a first dielectric layer covering the semiconductor substrate and the transistor gate; a source field plate on the first dielectric layer and coupled to a source field plate probe pad spaced from and electrically isolated from the source contact probe pad; and the source field plate capacitively coupled through the first dielectric layer to a first portion of the extended drain.

Aspects disclosed in the detailed description include an integrated circuit (IC) package employing a metal block with metal interconnects thermally coupling a semiconductor die (die) to an interposer substrate for dissipating thermal energy in the die. The die is coupled to a package substrate to provide signal routing paths to the die. To facilitate additional dies being stacked in the IC package as a three-dimensional (3D) IC (3DIC) package, the IC package also includes an interposer substrate adjacent to the die. The interposer substrate supports providing additional signal routing paths to the package substrate. The interposer substrate also includes a metal block which comprises a plurality of metal layers and is thermally coupled to the die and a metal interconnect(s) in the interposer substrate to dissipate thermal energy from the die through the metal block and through the coupled metal interconnect(s).

An apparatus including a substrate having a first surface, and a silicon interposer including a first surface and a second surface, wherein the first surface is connected to the first surface of the substrate. The apparatus also includes at least one stack including an artificial intelligence (AI) chiplet and a plurality of static random-access memories (SRAMs) stacked below the AI chiplet, wherein the at least one stack includes a top surface, a bottom surface, a first side surface and a second side surface, and the at least one stack is orthogonally attached by the first side surface to the second surface of the silicon interposer. The apparatus additionally includes a heat spreader surrounding the top surface, the bottom surface and the second side surface of the at least one stack.