A package structure includes a circuit substrate, a semiconductor package, a first ring structure and a second ring structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The first ring structure is attached to the circuit substrate and surrounding the semiconductor package, wherein the first ring structure includes a central opening and a plurality of corner openings extending out from corners of the central opening, the semiconductor package is located in the central opening, and the plurality of corner openings is surrounding corners of the semiconductor package.

A semiconductor package includes a metallic pad and leads, a semiconductor die including a semiconductor substrate attached to the metallic pad, and a conductor including a sacrificial fuse element above the semiconductor substrate, the sacrificial fuse element being electrically coupled between one of the leads and at least one terminal of the semiconductor die, a shock-absorbing material over a profile of the sacrificial fuse element, and mold compound covering the semiconductor die, the conductor, and the shock-absorbing material, and partially covering the metallic pad and leads, with the metallic pad and the leads exposed on an outer surface of the semiconductor package. Either a glass transition temperature of the shock-absorbing material or a melting point of the shock-absorbing material is lower than a melting point of the conductor.

A package structure is provided. The package structure includes a redistribution structure, and the redistribution structure has multiple insulating layers and multiple conductive features. The package structure also includes a semiconductor die and a device element over opposite surfaces of the redistribution structure. The package structure further includes a first protective layer at least partially surrounding the semiconductor die. In addition, the package structure includes a second protective layer at least partially surrounding the device element. The second protective layer is thicker than the first protective layer, and the second protective layer and the first protective layer have different coefficients of thermal expansion.

In an embodiment, a device includes: a first integrated circuit die comprising a semiconductor substrate and a first through-substrate via; a gap-fill dielectric around the first integrated circuit die, a surface of the gap-fill dielectric being substantially coplanar with an inactive surface of the semiconductor substrate and with a surface of the first through-substrate via; a dielectric layer on the surface of the gap-fill dielectric and the inactive surface of the semiconductor substrate; a first bond pad extending through the dielectric layer to contact the surface of the first through-substrate via, a width of the first bond pad being less than a width of the first through-substrate via; and a second integrated circuit die comprising a die connector bonded to the first bond pad.

A semiconductor device includes: an insulated circuit substrate including a base plate, a resin layer on the base plate, and a circuit pattern on the resin layer; a semiconductor chip that is rectangular and is bonded to the circuit pattern such that a side edge of the semiconductor chip is spaced inwardly from an outer peripheral edge of the circuit pattern by a predetermined distance; a case on the resin layer and surrounds the circuit pattern and the semiconductor chip; and a sealing material that covers the insulated circuit substrate and semiconductor chip and is surrounded by the case. The predetermined distance and thickness of the circuit pattern are greater than or equal to 0.1 of a length of one side of the semiconductor chip. A peripheral region of the case and a peripheral region of the resin layer are connected to each other via an adhesive layer.

A semiconductor device includes a substrate having a semiconductor chip mounted thereon, a heat dissipation plate having a front surface on which the substrate is disposed, a case including a side wall disposed on the front surface of the heat dissipation plate so as to surround a housing space accommodating the substrate therein together with the heat dissipation plate and a lid disposed on the side wall to cover the housing space, and a sealing member filling the housing space to seal the substrate. The lid has a through hole and a projection (or a groove) provided on the inner surface of the lid, configured to surround the through hole so as not to contact the sealing member such that the projection forms a plurality of circumferential patterns around the through hole in plan view.

A power semiconductor module arrangement comprises a substrate comprising a dielectric insulation layer, and a first metallization layer attached to the dielectric insulation layer, at least one semiconductor body mounted on the first metallization layer, and a first layer comprising an encapsulant, the first layer being arranged on the substrate and covering the first metallization layer the at least one semiconductor body, wherein the first layer is configured to release liquid or oil at temperatures exceeding a defined threshold temperature.

A power semiconductor module arrangement comprises a substrate comprising a dielectric insulation layer, and a first metallization layer attached to the dielectric insulation layer, at least one semiconductor body mounted on the first metallization layer, and a first layer comprising an encapsulant, the first layer being arranged on the substrate and covering the first metallization layer the at least one semiconductor body, wherein the first layer is configured to release liquid or oil at temperatures exceeding a defined threshold temperature.

A power semiconductor package includes a substrate, a power semiconductor chip arranged on the substrate, and an encapsulant encapsulating the power semiconductor chip. The encapsulant includes a voltage stabilizing additive. The voltage stabilizing additive is configured to minimize or eliminate partial discharges within the encapsulant.

A resin enclosure includes: an inner wall portion from a wall surface defining the space to a side surface of the lead terminal close to the space; and a covering portion that covers at least a part of a top surface of a first portion of the lead terminal.