Provided is a technique for enhancing the accuracy of deterioration diagnosis in a semiconductor device. The semiconductor device relating to the technique disclosed in the present specification is provided with a case, a semiconductor chip inside the case, a metal wire bonded to an upper surface of the semiconductor chip, at least one test piece inside the case, and a pair of terminals provided outside the case and connected to the test piece. The test piece is separated from the metal wire inside the case.

A semiconductor package includes a package substrate, a first semiconductor chip on an upper surface of the package substrate, a spacer chip on the upper surface of the package substrate and spaced apart from the first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the spacer chip by a plurality of adhesive films, respectively, and a molding member on the spacer chip, the first semiconductor chip, and the plurality of second semiconductor chips. When viewed in a plan view, the spacer chip has an overlapping region overlapping with a lowermost second semiconductor chip of the plurality of second semiconductor chips. The lowermost second semiconductor chip is attached to the spacer chip by a first adhesive film. A portion of the first adhesive film attached to the spacer chip is within a recess that is in an upper surface of the overlapping region of the spacer chip.

A power module includes a first end power semiconductor element and a second end power semiconductor element. A first sum is a sum of a path length between the gate electrode of the first end power semiconductor element and a first control terminal and a path length between the source electrode of the first end power semiconductor element and a first detection terminal. A second sum is a sum of a path length between the gate electrode of the second end power semiconductor element and the first control terminal and a path length between the source electrode of the second end power semiconductor element and the first detection terminal. The power module includes a first control layer connected to the gate electrode. The first control layer includes a first detour portion that detours the path to reduce a difference between the first sum and the second sum.

A semiconductor module includes a laminate substrate including an insulating plate and first and second circuit boards on an upper surface of the insulating plate, the first semiconductor device on an upper surface of the first circuit board, a first main terminal, and a first metal wiring board that electrically connects the first semiconductor device to the first main terminal. The first metal wiring board has a first bonding section bonded to an upper surface electrode of the first semiconductor device, a second bonding section bonded to an upper surface of the second circuit board, a first coupling section that couples the first bonding section to the second bonding section, a first raised section that rises upward from an end portion of the second bonding section. The first raised section has an upper end that is electrically connected to the first main terminal.

A semiconductor package assembly is provided. The semiconductor package assembly includes a substrate, an interposer, a first die, a second die, and a dummy die structure. The interposer is disposed on the substrate. The interposer includes a central region and a peripheral region. The peripheral region includes a corner region and a non-corner region. The first die is disposed on the interposer in the central region. The second die is disposed beside the first die and is located in the non-corner region of the peripheral region of the interposer. The dummy die structure is disposed beside the first die and the second die and is located in the corner region of the peripheral region of the interposer. The dummy die structure includes dummy dies stacked on each other in a first direction.

A semiconductor device assembly comprises an RDL including an external surface with external contacts, an internal surface with internal contacts, and conductors coupling the internal contacts to the external contacts. The assembly further includes a device connection layer having a first surface with first contact pads, a second surface with second contact pads, first conductive structures electrically coupling each of the first contact pads to a corresponding second contact pad, and a second plurality of conductive structures electrically coupling each of a first subset of the second plurality of contact pads to a corresponding contact pad of a second subset of the second plurality of contact pads. The assembly further includes stacks of semiconductor devices disposed between the RDL and the device connection layer, each stack in a cavity in a monolithic glass structure. The stacks electrically couple internal contacts to the first contact pads through TSVs in the stacks.

A method of manufacturing a power semiconductor device in accordance with an embodiment of the present disclosure may include providing a substrate disposed atop a heatsink, electrically connecting a semiconductor die to a top surface of the substrate, disposing a thin metallic layer atop the substrate, disposing a terminal atop the thin metallic layer, and performing a welding operation wherein a laser beam is directed at a top surface of the terminal to produce a plurality of weld connections connecting the terminal to the substrate, wherein the weld connections are separated by gaps, and wherein heat generated during the welding operation melts the thin metallic layer and molten material of the thin metallic flows into the gaps.

In examples, a semiconductor package includes a semiconductor die including a device side having circuitry formed therein and a non-device side opposite the device side. The semiconductor package includes a mold compound dam on the device side, the mold compound dam comprising a non-metallic material. The semiconductor package includes a mold compound on the device side of the semiconductor die and contacting an outer wall of the mold compound dam, the mold compound absent from a cavity defined by the mold compound dam.

A package structure includes a circuit substrate, a semiconductor package, a first ring structure and a second ring structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The first ring structure is attached to the circuit substrate and surrounding the semiconductor package, wherein the first ring structure includes a central opening and a plurality of corner openings extending out from corners of the central opening, the semiconductor package is located in the central opening, and the plurality of corner openings is surrounding corners of the semiconductor package.

An assembly for a power module includes an electrically isolating base body and first and second electrically conductive structures embedded in the base body. The first and electrically conductive structures are configured to carry different voltages during normal operation of the power module. The first and the second electrically conductive structure each comprise a first region that is not covered by the base body. The first region of the first conductive structure is arranged in a hole of the base body and is retracted with respect to an opening of the hole. The hole is filled with an electrically isolating material that covers the first region of the first conductive structure.