An assembly for a power module includes an electrically isolating base body and first and second electrically conductive structures embedded in the base body. The first and electrically conductive structures are configured to carry different voltages during normal operation of the power module. The first and the second electrically conductive structure each comprise a first region that is not covered by the base body. The first region of the first conductive structure is arranged in a hole of the base body and is retracted with respect to an opening of the hole. The hole is filled with an electrically isolating material that covers the first region of the first conductive structure.

According to one embodiment, a press contact type semiconductor device includes a first electrode, a second electrode, a pair of metal plates arranged between the first electrode and the second electrode, and a semiconductor element positioned between the pair of metal plates. The semiconductor element includes a semiconductor part with an electrode part on the upper surface of the semiconductor part. A metal sintered layer is between one of the metal plates and the electrode part. The surface area of the electrode part is less than the surface area of the metal plate.

A first semiconductor chip has a first surface in contact with a first circuit board and a second surface on which a second conductor is provided. A second semiconductor chip has a third surface in contact with a second circuit board and a fourth surface on which a third conductor is provided. A first pillar has a fifth surface in contact with the first circuit board. A second circuit board is in contact with a surface of a second conductor, a surface of a third conductor, and the first pillar. A plurality of insulating pillars extends in a direction connecting the first and second circuit boards and are in contact with the first and second circuit boards. A sealing body surrounds the first and second semiconductor chips, the first pillar, and the insulating pillars, and includes.

A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.

A package structure and a method of forming the same are provided. A method includes forming first electrical connectors and second electrical connectors on a first side of an interposer wafer. An integrated circuit die is bonded to the first side of the interposer wafer using the first electrical connectors. A stiffener structure is attached to the first side of the interposer wafer adjacent the integrated circuit die. The stiffener structure covers the second electrical connectors in a plan view. The integrated circuit die and the stiffener structure are encapsulated with a first encapsulant. The interposer wafer and the stiffener structure are singulated to form a stacked structure.

A semiconductor module comprises a substrate comprising a dielectric insulation layer and at least a first metallization layer arranged on the dielectric insulation layer, and a housing comprising sidewalls, the sidewalls defining an internal volume of the housing, wherein the housing is arranged such that the substrate is arranged within the internal volume defined by the sidewalls, with the metallization layer facing the internal volume of the housing, the housing comprises at least one mounting element for securely mounting the housing on a heat sink, and the sidewalls of the housing consist of an electrically conducting material.

A chip packaging structure includes, a chip on a substrate; an enclosure structure on the chip, a wall of the enclosure structure comprises a sealed cavity, and the chip is revealed through the sealed cavity; a layer of thermal interface material for the chip, formed by filling a liquid metal into the sealed cavity of the wall of the enclosure structure; and a heat sink, formed on the layer of thermal interface material, is hermetically sealed to the wall of the enclosure structure. The heat sink component is formed on the layer of the thermal interface material, sealed and connected to the enclosure structure. The enclosure structure using flexible materials to prevent the liquid metal from overflowing in the encapsulation and application process, thereby reducing degradation. The UV curing adhesive is used for sealing and fixing the connection to the thermal interface material layer, so the disassembly and replacement of the process is simpler.

An object is to provide a technique that lowers the self-inductance of a semiconductor device. A semiconductor device includes an insulating substrate having a circuit pattern formed on an upper surface thereof, a semiconductor element mounted on the upper surface of the circuit pattern, and a plurality of electrode terminals each having one end portion bonded to the upper surface of the circuit pattern. The electrode terminals having portions of mutual adjacency of the plurality of electrode terminals are coated with the insulating film having a thickness of less than 100 at least at the portions.

A package structure is provided. The package structure includes a substrate, a first electronic component, an encapsulant, and a protective element. The first electronic component is over the substrate. The encapsulant is over the substrate and defines a cavity that exposes the first electronic component. The protective element covers the first electronic component. A lateral surface of the protective element is substantially aligned with a lateral surface of the encapsulant.

An electronic device (e.g., a diode) is provided that includes a substrate and a patterned layer of superconducting material disposed over the substrate. The patterned layer forms a first electrode, a second electrode, and a loop coupling the first electrode with the second electrode by a first channel and a second channel. The first channel and the second channel have different minimum widths. For a range of current magnitudes, when a magnetic field is applied to the patterned layer of superconducting material, the conductance from the first electrode to the second electrode is greater than the conductance from the second electrode to the first electrode.