A semiconductor package may include: a device layer including a first semiconductor chip; a second semiconductor chip on the device layer; and a third semiconductor chip on the second semiconductor chip, wherein the device layer further includes: a molding layer surrounding the first semiconductor chip; a redistribution layer on the molding layer; and a conductive post beside the first semiconductor chip, the conductive post vertically penetrating the molding layer and connecting to the redistribution layer, wherein the redistribution layer includes: a first insulating pattern; a power delivery network (PDN) pattern in the first insulating pattern; and a redistribution pad exposed through an upper surface of the first insulating pattern, wherein the second semiconductor chip includes a first chip pad at an inactive surface of the second semiconductor chip, and wherein the PDN pattern is electrically connected to the second semiconductor chip through the redistribution pad and the first chip pad.

A semiconductor package includes a first semiconductor chip and a plurality of first through-electrodes passing through the first semiconductor substrate, a plurality of second semiconductor chips each including a second semiconductor substrate and a plurality of second through-electrodes passing through the second semiconductor substrate, the plurality of second semiconductor chips being stacked on the first semiconductor chip, a plurality of bonding pads disposed between the first semiconductor chip and the plurality of second semiconductor chips and electrically connecting the plurality of first through-electrodes to the plurality of second through-electrodes, a dummy chip attached to the plurality of second semiconductor chips, and, a package molding layer on the first semiconductor chip covering the first semiconductor chip, the plurality of second semiconductor chips, and the dummy chip, in which the dummy chip includes a plurality of trenches filled by a portion of the package molding layer.

A packaged module can include a packaging substrate having first and second side with a plurality of layers therebetween in a printed circuit board configuration and having a thickness that is less than 200 m, and a first-side portion including a first component mounted on the first side of the packaging substrate and a first mold structure implemented to at least partially encapsulate the first component. The packaged module can further include a second-side portion including a second component mounted on the second side of the packaging substrate and a plurality of conductive mounting structures. The second-side portion can further include a second mold structure implemented to at least partially encapsulate the second component, with the second mold structure further encapsulating the conductive mounting features while providing respective exposed mounting surfaces of the conductive mounting features.

A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

A substrate including a two-dimensional array of semiconductor dies and a rectangular grid of trenches that laterally extend along dicing channel regions may be provided. The rectangular grid of trenches may be filled with an elastic dielectric fill material. A combination of the two-dimensional array of semiconductor dies and a grid-shaped portion of the elastic dielectric fill material filling the rectangular grid of trenches may be diced along the dicing channel regions. A plurality of elastically padded semiconductor dies is formed. Each of the elastically padded semiconductor dies includes a respective singulated semiconductor die that includes semiconductor devices and metal bump structures located on dielectric material layers, and further includes an elastic protective material portion including a portion of the elastic dielectric fill material and laterally surrounding the dielectric material layers.

To improve performance of a semiconductor device. A semiconductor device includes a wiring substrate, a semiconductor chip mounted on a first upper surface of the wiring substrate, an electronic component mounted on the first upper surface, and a stiffener ring fixed to the first upper surface. The stiffener ring includes a first portion arranged to continuously surround a periphery of the semiconductor chip in plan view and adhering to the first upper surface of the wiring substrate, and a second portion connected to the first portion and arranged at a position spaced away from the first upper surface of the wiring substrate in plan view. The second portion of the stiffener ring partially overlaps the electronic component.

A semiconductor package may include a lower semiconductor chip; an upper semiconductor chip on the lower semiconductor chip, the upper semiconductor chip including a substrate having a first surface facing the lower semiconductor chip and a second surface opposing the first surface, and a measurement via pattern portion in a peripheral region of the substrate; and a sealing member covering the upper semiconductor chip on the lower semiconductor chip and exposing the second surface of the substrate. The measurement via pattern portion may include first dummy via structures extending from the first surface of the substrate to the second surface such that end portions thereof are exposed from the second surface of the substrate; and second dummy via structures extending from the first surface of the substrate to a depth such that end portions thereof are not exposed from the second surface of the substrate.

A system and method for forming a bonded integrated circuit, comprising dispensing a dielectric material on a first side of an integrated circuit, shaping the dielectric material on the first side of the integrated circuit to form a first dielectric surface; and dispensing a conductive material between a first printed circuit board (PCB) top surface and a top surface of the integrated circuit to form a first connection, the first connection situated on the first dielectric surface.

A device structure may be manufactured by forming metal interconnect structures embedded in dielectric material layers over a substrate; forming active metal connection structures, primary dummy metal structures, and miniature dummy metal structures over a topmost dielectric material layer selected from the dielectric material layers, wherein the miniature dummy metal structures have a lesser height than the active metal connection structures and the primary dummy metal structures; and forming bonding pads over the active metal connection structures, the primary dummy metal structures, and the miniature dummy metal structures, wherein the active metal connection structures and the primary dummy metal structures are contacted by the bonding pads, and the miniature dummy metal structures are not contacted by any of the bonding pads.

A semiconductor device and a method of forming the same are provided. The semiconductor device includes an integrated circuit die, a dielectric layer, an under-bump metallurgy layer, an interconnection die, and a solder material. The integrated circuit die includes a first die connector. The dielectric layer is located on the integrated circuit die. The under-bump metallurgy layer has a line portion on the dielectric layer and a via portion extending through the dielectric layer to contact the first die connector. The interconnection die includes a second die connector. The solder material is located between the line portion of the under-bump metallurgy layer and the second die connector. The under-bump metallurgy layer includes a first copper layer having a uniform grain orientation, wherein the top surface of the first copper layer is in direct contact with the solder material.