A package structure includes a circuit substrate, a semiconductor package, a first ring structure and a second ring structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The first ring structure is attached to the circuit substrate and surrounding the semiconductor package, wherein the first ring structure includes a central opening and a plurality of corner openings extending out from corners of the central opening, the semiconductor package is located in the central opening, and the plurality of corner openings is surrounding corners of the semiconductor package.

A composite component containing one or more electronic components. The composite component includes a Si base layer having a first main surface, and a second main surface facing the first main surface, a redistribution layer disposed on the first main surface, a through-Si via extending through the Si base layer and the adhesive layer to electrically connect the redistribution layer and the electronic component, and extending through the Si base layer, an electronic component electrically connected to the through-Si via, and disposed on the second main surface, sidewall portions surrounding the electronic component, and disposed to form a recessed portion together with the Si base layer, and a resin sealing portion sealing the electronic component.

A semiconductor package may include a first redistribution structure, a sub-semiconductor package on the first redistribution structure, where the sub-semiconductor package may include a second redistribution structure, a bridge die on the second redistribution structure, a first molding material configured to cover the bridge die on the second redistribution structure, a third redistribution structure on the first molding material and on the bridge die, a first semiconductor die on the third redistribution structure, a second semiconductor die on the third redistribution structure, and beside the first semiconductor die, where the second semiconductor die is electrically connected to the first semiconductor die through the bridge die, and a second molding material configured to cover the first semiconductor die and the second semiconductor die, on the third redistribution structure, and a third molding material configured to cover the sub-semiconductor package, on the first redistribution structure.

An integrated circuit package includes a substrate, a semiconductor interposer on the substrate, and a first integrated circuit chip on the interposer. The interposer includes a galvanic effect test structure including a test contact pad and a detection contact pad. The interposer includes a plurality of primary contact pads electrically coupled to the first integrated circuit chip. The galvanic effect structure can be utilized to test the interposer for galvanic corrosion prior to assembling the interposer into the integrated circuit package.

A packaged lateral semiconductor device includes a resistor connected between the device substrate and a package ground point. The packaged device avoids the drawbacks of a floating substrate, and reduces substrate leakage current and increases breakdown voltage relative to conventionally packaged structures. Moreover, device substrate leakage current and breakdown voltage may be controlled by selecting a value of the resistor. Exemplary devices include high voltage lateral devices such as high-electron mobility transistors (HEMTs), implemented in technologies such as GaN or GaAs, where the packaging achieves high breakdown voltage with improved dynamic behavior.

A method of manufacturing a semiconductor device is provided. A permalloy device is received. An interposer die is formed. A semiconductor die is bonded to the interposer die. A conductive coil is formed over a substrate. The conductive coil includes a bottom metal layer over the substrate, a middle metal layer and a top metal layer interconnected to each other. The permalloy device is disposed over the bottom metal layer through a pick and place operation. An inter-metal-dielectric layer is formed to laterally surround the permalloy device before forming the middle metal layer of the conductive coil. The permalloy device has a polygonal ring shape wrapped with the conductive coil.

An embodiment semiconductor device may include a semiconductor die; one or more redistribution layers formed on a surface of the semiconductor die and electrically coupled to the semiconductor die; and an active or passive electrical device electrically coupled to the one or more redistribution layers. The active or passive electrical device may include a silicon substrate and a through-silicon-via formed in the silicon substrate. The active or passive electrical device may be configured as an integrated passive device including a deep trench capacitor or as a local silicon interconnect. The semiconductor device may further include a molding material matrix formed on a surface of the one or more redistribution layers such that the molding material matrix partially or completely surrounds the active or passive electrical device.

Methods and structures relating to bonding wafers using an aluminum nitride bonding layer with embedded metallization features. In some embodiments, the method may comprise forming a bonding layer on a first wafer where the bonding layer is formed of epitaxially grown aluminum nitride and where the first wafer is a silicon-based material and forming one or more metal features into the bonding layer on the first wafer. The first wafer may be hybrid bonded to a second wafer or die with one or more second metal features surrounded by a diffusion barrier layer. The one or more second metal features of the second wafer or die bonds to the one or more metal features of the first wafer. The diffusion barrier layer of the second wafer or die bonds, at least, to the bonding layer of the first wafer.

Methods and structures relating to bonding wafers using an aluminum nitride bonding layer. In some embodiments, the method may comprise forming a bonding layer of aluminum nitride on a first wafer where the aluminum nitride is grown epitaxially onto the first wafer and bonding the first wafer to a second wafer or die using a low temperature bonding process of less than 400 degrees Celsius. The aluminum nitride may be epitaxially grown using a physical vapor deposition (PVD) process, a metal organic chemical vapor deposition (MOCVD) process, or a molecular-beam epitaxy (MBE) process. The carrier wafer may be silicon with a (111) crystal structure orientation or 4H-silicon carbide with a (001) crystal structure orientation at the interface with the bonding layer.

A semiconductor package includes a package base substrate including a potential plate. An interposer is arranged on the package base substrate and comprises at least one interposer through electrode, at least one first connection bump, and at least one second connection bump. A first stacked chip unit is arranged on the interposer and comprises a first semiconductor chip and at least one second semiconductor chips arranged on the first semiconductor chip. At least one passive device unit is arranged on the package base substrate. The at least one passive device unit is spaced apart from the interposer in a horizontal direction parallel to an upper surface of the package base substrate. The at least one first connection bump is a dummy bump. The potential plate electrically connects the at least one first connection bump and a power terminal of the at least one passive device unit to each other.