An interposer device includes a core substrate, at least one embedded component formed within the core substrate, and at least one redistribution layer (RDL) on at least one of a first surface of the core substrate or a second surface of the core substrate opposite the first surface.

A method includes: forming an interposer die using a substrate, the interposer die including a plurality of conductive vias in the substrate; bonding the interposer die to a first redistribution layer (RDL); encapsulating the interposer die; forming a second RDL over the interposer die on a side opposite to the first RDL; bonding a first semiconductor die with one of the first RDL and the second RDL; and encapsulating the first semiconductor die.

A package structure includes a circuit substrate, a semiconductor package, a first ring structure and a second ring structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The first ring structure is attached to the circuit substrate and surrounding the semiconductor package, wherein the first ring structure includes a central opening and a plurality of corner openings extending out from corners of the central opening, the semiconductor package is located in the central opening, and the plurality of corner openings is surrounding corners of the semiconductor package.

A method of fabricating integrated passive device dies includes forming a first plurality of integrated passive devices on a substrate, forming a plurality of micro-bumps on the first plurality of integrated passive devices such that the plurality of micro-bumps act as electrical connections to the integrated passive devices, and dicing the substrate to form an integrated passive device die including a second plurality of integrated passive devices. The micro-bumps may be formed in an array or staggered configuration and may have a pitch that is in a range from 20 microns to 100 microns. The integrated passive devices may each include a seal ring and the integrated passive device die may have an area that is a multiple of an integrated passive device area. The method may further include dicing the substrate in various ways to generate integrated passive device dies having different sizes and numbers of integrated passive devices.

A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer. The third patterned conductive layer is on the second patterned conductive layer, and the connector is directly on the third patterned conductive layer.

An interfacial structure, along with methods of forming such, are described. The structure includes a first interfacial layer having a first dielectric layer, a first conductive feature disposed in the first dielectric layer, and a first thermal conductive layer disposed on the first dielectric layer. The structure further includes a second interfacial layer disposed on the first interfacial layer. The second interfacial layer is a mirror image of the first interfacial layer with respect to an interface between the first interfacial layer and the second interfacial layer. The second interfacial layer includes a second thermal conductive layer disposed on the first thermal conductive layer, a second dielectric layer disposed on the second thermal conductive layer, and a second conductive feature disposed in the second dielectric layer.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a surface; a second die having a first surface, an opposing second surface, and side surfaces between the first surface and the second surface, wherein the first surface of the second die is electrically coupled to the surface of the first die, and wherein the side surfaces of the second die are scalloped. In some embodiments, side surfaces of the second die may include a protective coating material, where the protective coating material includes an alkyl silane, a fluoroalkyl silane, a thiol, a phosphonic acid, an alkanoic acid, a siloxane, a silazane, a polyolefin, or a fluorinated polymer. In some embodiments, a microelectronic assembly may further include a dielectric material around a plurality of second dies and the dielectric material does not have an interface seam.

A semiconductor package includes: a redistribution layer including an upper surface and a lower surface opposite to each other in a first direction; a semiconductor chip disposed on the upper surface of the redistribution layer; a bridge die disposed on the lower surface of the redistribution layer, and electrically connected to the semiconductor chip, wherein the bridge die includes a first surface and a second surface, wherein the first surface faces the semiconductor chip, and the second surface is opposite to the first surface in the first direction; a mold film disposed on a third surface of the bridge die; and a protective film disposed on the second surface of the bridge die.

A semiconductor package may include: a first semiconductor chip including a first substrate including a first front surface opposite to a first rear surface, first front pads on the first front surface, first through-electrodes electrically connected to the first front pads, and first rear pads on the first through-electrodes, the first through-electrodes penetrating the first substrate and protruding to the first rear surface; a first step structure including a first dummy substrate, a first buffer layer on the first dummy substrate, and a first cavity penetrating the first dummy substrate and the first buffer layer, with the first semiconductor chip in the first cavity; and a first dielectric layer on at least portions of the first semiconductor chip and the first step structure, and around the first through-electrodes and the first rear pads on the first rear surface of the first substrate.

An electronic device includes a substrate, a base substrate, a metal connection body, a support body, a metal body, and a via. The substrate includes one main surface with a functional element and is a piezoelectric substrate or a compound semiconductor substrate. The substrate is mounted on the base substrate such that the one main surface faces the base substrate. The metal body is in contact with the support body and includes at least a portion extending to outside the substrate in plan view from the support body. The via connects the portion of the metal body outside the substrate and the base substrate to each other and has a higher thermal conductivity than the substrate.