According to one embodiment, a semiconductor memory device includes a first chip; and a second chip electrically connected to the first chip via a first connection pad, the second chip including a memory cell array, a first contact electrically connected to the first connection pad, and a first interconnect including a first coupling portion electrically connected to an upper end of the first contact, and a first extension continuously extending from the first coupling portion above an upper surface of the source line, wherein the first coupling portion has a shape in which a trench above the first contact is filled up to a level of a lower surface of the first extension, and the first coupling portion includes a lower surface at a level below the upper surface of the source line.

The present disclosure provides a semiconductor package structure and a fabrication method thereof. The semiconductor package structure includes: a plurality of first semiconductor chips arranged as being stacked along a first direction, wherein the first semiconductor chip includes at least one conductive structure; the conductive structure includes a first connection structure and a second connection structure both extending along the first direction, and an interconnection structure located between the first connection structure and the second connection structure in the first direction; and the interconnection structure is connected with both the first connection structure and the second connection structure; and a first hybrid bonding layer located between two adjacent ones of the first semiconductor chips in the first direction, wherein the first hybrid bonding layer includes at least one first bonding structure coupled with the conductive structures in the two adjacent ones of the first semiconductor chips.

Provided is a semiconductor device including a peripheral circuit structure comprising peripheral circuits and a cell array structure overlapping the peripheral circuit structure and comprising first and second cell array regions and a connection region therebetween in a first direction, the cell array structure including a buried insulating pattern in the connection region, the buried insulating pattern having first and second side surfaces facing each other in the first direction and a third side surface connecting the first and second side surfaces, a stack including vertically stacked conductive patterns, each of the conductive patterns including a horizontal portion parallel to the first direction and a pad portion inclined with respect to the horizontal portion, and cell contact plugs connected to the pad portions of the conductive patterns, respectively, and the pad portion of each conductive pattern being on the first, second, and third side surfaces of the buried insulating pattern.

A method according to the present disclosure includes providing a first workpiece that includes a first substrate and a first interconnect structure, providing a second workpiece that includes a second substrate, a second interconnect structure, and a through via extending through a portion of the second substrate and a portion of the second interconnect structure, forming a first bonding layer on the first interconnect structure, forming a second bonding layer on the second interconnect structure, bonding the second workpiece to the first workpiece by directly bonding the second bonding layer to the first bonding layer, thinning the second substrate, forming a protective film over the thinned second substrate, forming a backside via opening through the protective film and the thinned second substrate to expose the through via, and forming a backside through via in the backside via opening to physically couple to the through via.

A semiconductor package comprises a first die having a central region and a peripheral region that surrounds the central region; a plurality of through electrodes that penetrate the first die; a plurality of first pads at a top surface of the first die and coupled to the through electrodes; a second die on the first die; a plurality of second pads at a bottom surface of the second die, the bottom surface of the second die facing the top surface of the first die; a plurality of connection terminals that connect the first pads to the second pads; and a dielectric layer that fills a space between the first die and the second die and surrounds the connection terminals. A first width of each of the first pads in the central region may be greater than a second width of each of the first pads in the peripheral region.

Methods, systems, and devices for polymer material gap-fill for hybrid bonding in a stacked semiconductor system are described. A stacked semiconductor may include a first semiconductor die on a semiconductor wafer. A polymer material may be on the semiconductor wafer and may at least partially surround the first semiconductor die. A silicon nitride material may be on the first semiconductor die and on the polymer material. And a second semiconductor die may be hybrid bonded with a bonding material on the silicon nitride material.

Various embodiments of fanout packages are disclosed. A method of forming a microelectronic assembly is disclosed. The method can include bonding a first surface of at least one microelectronic substrate to a surface of a carrier using a direct bonding technique without an intervening adhesive, the microelectronic substrate having a plurality of conductive interconnections on at least one surface of the microelectronic substrate. The method can include applying a molding material to an area of the surface of the carrier surrounding the microelectronic substrate to form a reconstituted substrate. The method can include processing the microelectronic substrate. The method can include singulating the reconstituted substrate at the area of the surface of the carrier and at the molding material to form the microelectronic assembly.

A three-dimensional (3D) laminated chip that includes a first semiconductor chip including a first through electrode disposed therein. A second semiconductor chip is arranged horizontally adjacent to the first semiconductor chip. A third semiconductor chip is arranged on the first semiconductor chip and the second semiconductor chip. A size of the third semiconductor chip is greater than a size of the first semiconductor chip.

A semiconductor die includes semiconductor devices located on a semiconductor substrate, metal-insulator-metal corner structures overlying the semiconductor devices and located in corner regions of the semiconductor die. Metal-insulator-metal corner structures are located in the corner regions of the semiconductor die. Each of the metal-insulator-metal corner structures has a horizontal cross-sectional shape selected from a triangular shape and a polygonal shape including a pair of laterally-extending strips extending along two horizontal directions that are perpendicular to each other and connected to each other by a connecting shape.

A semiconductor device includes a memory cell structure in a cell array region, an electrode stacking structure including a plurality of electrodes and a plurality of interlayer insulation layers alternately stacked in a connection region, and a plurality of electrode contact portions penetrating at least a partial portion of the electrode stacking structure and are electrically connected to the plurality of electrodes. The plurality of electrode contact portions include first and second contact portions. The first contact portion includes a first conductive portion, and a first side insulation layer between the electrode stacking structure and the first conductive portion. The second contact portion includes a second conductive portion, and a second side insulation layer between the electrode stacking structure and the second conductive portion. The second side insulation layer has a shape or a structure different from a shape or a structure of the first side insulation layer.