In an embodiment, a device includes: an integrated circuit die including a die connector; a dielectric layer on the integrated circuit die; an under-bump metallurgy layer having a line portion on the dielectric layer and having a via portion extending through the dielectric layer to contact the die connector; a through via on the line portion of the under-bump metallurgy layer, the through via having a first curved sidewall proximate the die connector, the through via having a second curved sidewall distal the die connector, the first curved sidewall having a longer arc length than the second curved sidewall; and an encapsulant around the through via and the under-bump metallurgy layer.

The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.

A method of making a semiconductor device may include providing a large semiconductor die comprising conductive interconnects with a first encapsulant disposed over four side surfaces of the large semiconductor die, over the active surface of the large semiconductor die, and around the conductive interconnects. A first build-up interconnect structure may be formed over the large semiconductor die and over the first encapsulant. Vertical conductive interconnects may be formed over the first build-up interconnect structure and around an embedded device mount site. An embedded device comprising through silicon vias (TSVs) may be disposed over the embedded device mount site. A second encapsulant may be disposed over the build-up structure, and around at least five sides of the embedded device. A second build-up structure may be formed disposed over the planar surface and configured to be electrically coupled to the TSVs of the embedded device and the vertical conductive interconnects.

Techniques are provided herein to form an integrated circuit having stacked semiconductor devices with their source or drain regions coupled together via matching backside connections. In an example, FET (field effect transistor) devices may be formed on two different substrates and bonded together at their backsides such that backside contacts beneath each device substantially align at or near the bonding interface. The substrate beneath both the first FET and the second FET is removed, and backside contacts are formed beneath the source or drain regions of the first and second FETs. A bonding layer may also be formed on the backside of either the first FET or the second FET. The second FET is then flipped upside down and bonded to the backside of the first FET, such that the backside contacts from the first and second FET's are substantially aligned and are conductively coupled through the bonding layer.

A semiconductor memory device may include a substrate including a cell array region and an extension region, a plurality of gate electrodes alternately stacked in a first direction on the substrate and in a staircase structure on the extension region, a channel structure penetrating through the plurality of gate electrodes on the cell array region and extending in the first direction, a through via penetrating through a first gate electrode of the plurality of gate electrodes and a second gate electrode of the plurality of gate electrodes, and the second gate electrode being between the first gate electrode and the substrate, the through via connecting to the first gate electrode, and an insulating pattern between the second gate electrode and the through via. The insulating pattern includes an insulating structure on a sidewall of the second gate electrode.

A semiconductor memory device includes a substrate including a cell array region and an extension region, gate electrodes on the substrate, a channel structure on the cell array region, and an insulating pattern. The gate electrodes are alternately stacked in a first direction, providing a staircase structure on the extension region. The channel structure penetrates the gate electrodes. A first through via penetrates first and second gate electrodes. The first through via, disposed between the first gate electrode and the substrate, is connected to the first gate electrode. The insulating pattern includes: an insulating structure; a liner insulating layer; and a capping pattern disposed between the insulating structure and a sidewall of the first through via. A width of a capping layer of the capping pattern decreases as a distance from the first through via increases.

A device includes a plate layer; gate electrodes including first gate electrodes stacked on the plate layer and a second gate electrode on the first gate electrodes; a first channel structure extending through the first gate electrodes and including a first channel layer; a second channel structure extending through the second gate electrode and including a second channel layer; a channel connection portion on an uppermost surface of the first channel structure and electrically connecting the first channel layer to the second channel layer; and a horizontal insulating layer extending between an uppermost first gate electrode and the second gate electrode, wherein the horizontal insulating layer is on a level different from a level of the channel connection portion, and wherein the channel connection portion covers a portion of a lower surface of the second channel structure and exposes a portion of the lower surface of the second channel structure.

An integrated circuit (IC) is described. The IC includes a substrate supporting a buried oxide (BOX) layer. The IC also includes a first-type semiconductor layer on the BOX layer. The IC further includes an oxide layer on the first-type semiconductor layer. The IC also includes a second-type semiconductor layer on the oxide layer, in which a perforated portion of the first-type semiconductor layer is exposed through an opening in the second-type semiconductor layer and the oxide layer. The IC further includes a contact between the first-type semiconductor layer and the second-type semiconductor layer. The IC also includes the BOX layer defining a cavity and partially in the substrate.

A semiconductor device assembly comprises an RDL including an external surface with external contacts, an internal surface with internal contacts, and conductors coupling the internal contacts to the external contacts. The assembly further includes a device connection layer having a first surface with first contact pads, a second surface with second contact pads, first conductive structures electrically coupling each of the first contact pads to a corresponding second contact pad, and a second plurality of conductive structures electrically coupling each of a first subset of the second plurality of contact pads to a corresponding contact pad of a second subset of the second plurality of contact pads. The assembly further includes stacks of semiconductor devices disposed between the RDL and the device connection layer, each stack in a cavity in a monolithic glass structure. The stacks electrically couple internal contacts to the first contact pads through TSVs in the stacks.

A method of manufacturing a semiconductor device includes forming a cell chip including a first substrate, a source layer on the first substrate, a stacked structure on the source layer, and a channel layer passing through the stacked structure and coupled to the source layer, flipping the cell chip, exposing a rear surface of the source layer by removing the first substrate from the cell chip, performing surface treatment on the rear surface of the source layer to reduce a resistance of the source layer, forming a peripheral circuit chip including a second substrate and a circuit on the second substrate, and bonding the cell chip including the source layer with a reduced resistance to the peripheral circuit chip.