A semiconductor package according to an embodiment includes a substrate; a protective layer disposed on the substrate; a first adhesive member disposed on the protective layer and having an open loop shape along a circumferential direction of an upper surface of the protective layer; and a cover member disposed on the first adhesive member, wherein a lower surface of the cover member includes: a first lower surface that contacts the first adhesive member, and a second lower surface that does not contact the first adhesive member, and the protective layer includes a first opening that vertically overlaps the second lower surface of the cover member and does not vertically overlap the first adhesive member.

An integrated circuit package includes a substrate, a semiconductor interposer on the substrate, and a first integrated circuit chip on the interposer. The interposer includes a galvanic effect test structure including a test contact pad and a detection contact pad. The interposer includes a plurality of primary contact pads electrically coupled to the first integrated circuit chip. The galvanic effect structure can be utilized to test the interposer for galvanic corrosion prior to assembling the interposer into the integrated circuit package.

Provided is a semiconductor package including a substrate including a body having a first surface and a second surface, the first surface and the second surface opposite to each other, a plurality of interconnection patterns arranged in a vertical direction within the body, the plurality of interconnection patterns including upper terminals on the first surface and lower terminals on the second surface, and an induction heating structure within the body, and the induction heating structure spaced apart from the plurality of interconnection patterns, an upper protective layer on the first surface of the substrate and the upper protective layer including first openings respectively exposing the upper terminals, a semiconductor chip on the upper protective layer, and the semiconductor chip including connection pads.

A die includes a substrate, a conductive pad, a connector a protection layer, and a passivation layer. The conductive pad is disposed over the substrate. The connector is disposed on the conductive pad. The connector comprises a seed layer and a conductive post on the seed layer. The protection layer laterally covers the connector. The passivation layer is disposed between the protection layer and the conductive pad. The conductive post is separated from the passivation layer and the protection layer by the seed layer.

A heat spreader is described that may include a substrate of a top device, and that cools the top die of a flip-chipped die combination. The heat spreader includes a material with a high thermal conductivity, such as a material including diamond. The top heat spreader substrate may have a connection to the bottom base substrate, e.g., carrier.

A package comprising an integrated device and a substrate coupled to the integrated device, wherein the substrate comprises a plurality of via interconnects, and wherein at least one via interconnect from the plurality of via interconnects comprises a planar cross sectional shape that includes a concave portion.

A package substrate includes a plurality of layers, each layer of the plurality of layers including a respective conductive pattern. The plurality of layers includes a first layer in which a first conductive pattern and a plurality of pads exposed externally with respect to the package substrate are disposed, a second layer located above the first layer, and including a second conductive pattern and a floating wiring pattern having an area overlapping the plurality of pads, and a third layer located above the second layer, and including a third conductive pattern.

A semiconductor package substrate includes a base substrate including a mounting area and a peripheral arca, at least one protrusion disposed between the mounting area and the peripheral area and protruding from the base substrate, and a resin inserted into a part of the base substrate and disposed around the at least one protrusion.

A semiconductor package includes a package substrate including an upper surface layer including a first surface area having a first surface roughness, and a second surface area having a second surface roughness less than the first surface roughness, and an interposer module mounted on the upper surface layer of the package substrate in the second surface area. The semiconductor package may also include an interposer including an upper surface layer including a first surface area having a first surface roughness, and a second surface area having a second surface roughness less than the first surface roughness. The semiconductor package may also include an printed circuit board substrate including an upper surface layer including a first surface area having a first surface roughness, and a second surface area having a second surface roughness less than the first surface roughness.

A semiconductor module may include a package substrate including a first surface and an opposite second surface, a semiconductor chip on the first surface of the package substrate, a plurality of pads on the second surface of the package substrate, and a plurality of solder balls connected to the plurality of pads, respectively, where the package substrate may include a slit in or on the second surface, at least a portion of the slit is disposed between the plurality of solder balls, the slit is spaced apart from the plurality of pads, and a filling layer is in the slit.