A semiconductor package includes a first redistribution substrate comprising a plurality of upper substrate pads including a first upper substrate pad;, a first semiconductor device mounted on the first redistribution substrate and connected to the first redistribution substrate through bonding of the first upper substrate pad to a first connection terminal, a plurality of conductive through posts disposed on the first redistribution substrate outside of the first semiconductor device from a plan view, and a second redistribution substrate disposed on the first semiconductor device and the plurality of conductive through posts. The first upper substrate pad has a convex upper surface and has a coupling roughness formed on an upper surface thereof.

Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate and the components are connected with conductive material in preformed holes in dielectric material in the bond lines aligned with TSVs of the devices and the exposed conductors of the substrate. Methods of fabrication are also disclosed.

Stacked semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate having at least a first layer and a second layer, an interconnect extending through the package substrate, a stack of dies carried by the package substrate, and one or more wirebonds electrically coupling the stack of dies to package substrate. Each of the layers of the package substrate can include a section of the interconnect with a frustoconical shape. Each of the sections can be directly coupled together. Further, the section in an uppermost layer of the package substrate is exposed at an upper surface of the package substrate. The wirebonds can be directly coupled to the exposed surface of the uppermost section.

Disclosed herein are microelectronic assemblies and related devices and methods for alleviating crack formation and propagation in glass by providing various edge features during or after singulation of a glass panel into individual glass units. In some embodiments, a microelectronic assembly includes a glass core (e.g., a layer of glass including a rectangular prism volume) having a first face, a second face opposite the first face, and an edge between an end of the first face and an end of the second face, and further includes a protection coating on the edge, where a material of the protection coating includes a low-density polystyrene foam, an ionogel, a fiber reinforced resin, a pre-impregnated dielectric, a pre-impregnated fabric, a carbon nanotube reinforced epoxy resin, a metal oxide, a mold material, or a solder resist.

Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a first surface, a second surface opposite the first surface, and a side surface extending between the first surface and the second surface, wherein the side surface protrudes at a middle of the glass layer; a dielectric layer at the first surface of the glass layer; and a recess in the dielectric layer at the first surface of the glass layer. In other embodiments, a microelectronic assembly may include a dielectric layer at a surface of a glass layer and a material along a side surface of the dielectric layer, the material including a dry film photoresist, a water-soluble material, a thermal decomposable material, or a non-filled polymeric material. In other embodiments, the dielectric layer may include a conductive bulk material along a side surface.

The disclosure describes a semiconductor device and a method for fabricating a semiconductor device. The semiconductor device includes: a first module and a second module stacked vertically on the first module, each module includes multiple dies stacked vertically within an insulation layer, wherein each die higher than a lower die is laterally offset from the lower die forming a terraced structure, wherein the second module comprises vertical wires connecting the overhang portions of the terraced structure of the second module to a top dielectric layer of the first module underneath the second module, and the insulation layer of the first module further includes through-insulation vias (TIVs) connecting the top dielectric layer to a bottom dielectric layer through the insulation layer, such that the dies of the second module are coupled to the bottom dielectric layer of the first module through the top dielectric layer and TIVs.

A semiconductor package may include a package substrate including first and second surfaces, which are opposite to each other, a first semiconductor chip on the first surface, a first mold layer on the first surface of the package substrate and top and side surfaces of the first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on the second surface, a second mold layer on the second surface of the package substrate, bottom and side surfaces of the second semiconductor chip, and bottom and side surfaces of the third semiconductor chip, a vertical conductive pillar provided to penetrate the second mold layer in a vertical direction and horizontally spaced apart from the second and third semiconductor chips, and connection terminals between a bottom surface of the first semiconductor chip and the first surface. The vertical conductive pillar may be placed on the second surface.

A package includes a first die, a second die, an encapsulant, and through insulating vias (TIV). The first die has a first bonding structure. The first bonding structure includes a first dielectric layer and first connectors embedded in the first dielectric layer. The second die has a semiconductor substrate and a second bonding structure over the semiconductor substrate. The second bonding structure includes a second dielectric layer and second connectors embedded in the second dielectric layer. Sidewalls of the second dielectric layer are aligned with sidewalls of the semiconductor substrate. The first connectors are in physical contact with the second connectors. The first connectors and the second connectors are arranged on two opposite sides of an interface between the first dielectric layer and the second dielectric layer. The encapsulant laterally encapsulates the second die. The TIVs are aside the second die.

A semiconductor package may include a buffer die including a plurality of first wire bonding pads, a first group of core dies sequentially stacked on the buffer die, a first interposer on the first group of core dies and including a plurality of first lower connection pads in a lower surface of the first interposer to face the plurality of first wire bonding pads, respectively, a plurality of first conductive wires extending vertically from the plurality of first wire bonding pads between the buffer die and the first interposer, the plurality of first conductive wires being connected to the plurality of first lower connection pads, respectively, and a second group of core dies sequentially stacked on the first interposer.

A semiconductor device and a method of making the same are provided. A first die and a second die are placed over a carrier substrate. A first molding material is formed adjacent to the first die and the second die. A first redistribution layer is formed overlying the first molding material. A through via is formed over the first redistribution layer. A package component is on the first redistribution layer next to the copper pillar. The package component includes a second redistribution layer. The package component is positioned so that it overlies both the first die and the second die in part. A second molding material is formed adjacent to the package component and the first copper pillar. A third redistribution layer is formed overlying the second molding material. The second redistribution layer is placed on a substrate and bonded to the substrate.