An integrated circuit package and the method of forming are provided. The integrated circuit package may include a first redistribution structure, a first bridge die over the first redistribution structure, a first encapsulant around the first bridge die, a second redistribution structure over the first bridge die and the first encapsulant, a first logic die, a second logic die, and a first input/output (I/O) die over the second redistribution structure, and a second encapsulant around the first logic die, the second logic die, and the first I/O die. The first I/O die may be between the first logic die and the second logic die in a top-down view. The first bridge die may electrically connect the first redistribution structure to the second redistribution structure. The first I/O die may electrically connect the first logic die to the second logic die.

A semiconductor package is provided. The semiconductor package includes a first die and a second die bonded to the first die. An encapsulant laterally encapsulates the second die. Through vias are disposed in the encapsulant. An interconnect structure is disposed on the second die, the through vias and the encapsulant. A redistribution structure is disposed on the interconnect structure. An inductor is embedded in the redistribution structure and the interconnect structure, wherein the inductor includes a portion of a metallization pattern of the redistribution structure and a portion of a conductive pattern of the interconnect structure. The portion of the metallization pattern of the inductor is adjacent to and substantially overlapped with the portion of the conductive pattern of the inductor. A manufacturing method of a semiconductor package is also provided.

A semiconductor package includes a package substrate, a bridge chip structure including a plurality of bridge chips that are accommodated in the package substrate and stacked in a vertical direction, and a plurality of semiconductor chips that are arranged on the package substrate and are electrically connected to each other through the bridge chip structure, wherein each of the plurality of bridge chips has different sizes.

A stack package, and a method of manufacturing the same, includes a first encapsulant layer formed on a carrier. Also semiconductor dies are sequentially offset stacked on the first encapsulant layer. Vertical connectors connected to the semiconductor dies are formed. A second encapsulant layer coupled to the first encapsulant layer is formed to encapsulate the vertical connectors and the semiconductor dies. Redistribution layers connected to the vertical connectors are formed on the second encapsulant layer.

Example embodiments are directed to a semiconductor package for improving Signal Integrity (SI) characteristics. The semiconductor package includes a package substrate, a mediate substrate arranged on the package substrate and including an active layer and a wiring layer, and at least two semiconductor devices on the mediate substrate. The wiring layer includes path wirings configured to connect the at least two semiconductor devices to each other. The path wirings include n paths (n is an integer that is 2 or more), and the active layer includes a selection circuit configured to select one of the n paths.

A method for fabricating semiconductor device includes the steps of first providing a first substrate having a high-voltage (HV) region and a medium voltage (MV) region and a second substrate having a low-voltage (LV) region and a static random access memory (SRAM) region, in which the HV region includes a HV device, the MV region includes a MV device, the LV region includes a fin field-effect transistor (FinFET), and the SRAM region includes a SRAM device. Next, a bonding process is conducted by using hybrid bonding, through-silicon interposer (TSI) or redistribution layer (RDL) for bonding the first substrate and the second substrate.

An electronic device comprises a substrate, an electronic element, a columnar portion and a sealing resin. The substrate includes an insulating layer having an insulating layer obverse surface facing a first side in a thickness direction and an insulating layer reverse surface, and a conductive portion exposed from the insulating layer obverse surface and the insulating layer reverse surface. The electronic element includes an element body having an element obverse surface facing the insulating layer obverse surface in the thickness direction, and electrodes disposed on the element obverse surface. The electrodes are electrically bonded to the conductive portion. The columnar portion projects from the conductive portion toward the first side in the thickness direction and has electrical conductivity. The sealing resin covers the insulating layer obverse surface, the electronic element, and the columnar portion.

A semiconductor package includes a redistribution layer, a first substrate disposed on the redistribution layer and having a first cavity, a first semiconductor chip in the first cavity and having a first connection pad, a first encapsulant covering the first semiconductor chip and filling the first cavity, a second substrate disposed on the first substrate and having a second cavity, a second semiconductor chip in the second cavity and having a second connection pad, a second encapsulant covering the second semiconductor chip and filling the second cavity, a first connection via penetrating through the first encapsulant, directly connected to the first connection pad, and connecting the first connection pad to the redistribution layer, and a second connection via penetrating through the first substrate and the first and second encapsulants, directly connected to the second connection pad, and connecting the second connection pad to the redistribution layer.

A method includes bonding a tier-1 device die to a carrier, forming a first gap-filling region to encapsulate the tier-1 device die, forming a first redistribution structure over and electrically connected to the tier-1 device die, and bonding a tier-2 device die to the tier-1 device die. The tier-2 device die is over the tier-1 device die, and the tier-2 device die extends laterally beyond a corresponding edge of the tier-1 device die. The method further includes forming a second gap-filling region to encapsulate the tier-2 device die, removing the carrier, and forming a through-dielectric via penetrating through the first gap-filling region. The through-dielectric via is overlapped by, and is electrically connected to, the tier-2 device die. A second redistribution structure is formed, wherein the first redistribution structure and the second redistribution structure are on opposing sides of the tier-1 device die.

A semiconductor package according to some example embodiments includes a substrate, a first semiconductor chip and a plurality of memory structures on the substrate, and a through via penetrating at least one of the plurality of memory structures. The plurality of memory structures are stacked in a vertical direction, the vertical direction being perpendicular to an upper surface of the substrate, each of the plurality of memory structures includes a buffer die, a plurality of memory dies stacked on the buffer die, and a molding member covering the buffer die and the plurality of memory dies, and the through via includes a mold through via that penetrates the molding member.