Molded device packages which allow electrical contacts to coupled to a first surface of a circuit substrate such as a printed circuit board while allowing the opposite surface to remain exposed for other purposes such as bonding thermal structures such as heatsinks include electrically-conductive pillars which are bonded to the first surface of the substrate and encapsulated in molding material. The molding material can one or more cavities over disposed over the first surface of the substrate which can be evacuated or gas-filled. The electrically-conductive pillars protrude from connected manifold and are joined to each other by a frame portion of the manifold. The manifold is patterned with a masking material that protects the pillars from being etched during a selective etching process which removes the frame portion of the manifold to separate the electrically-conductive pillars from each other.

An object is to provide a semiconductor module capable achieving both a heat radiation property and an insulation property. A semiconductor module includes: a substrate having a main surface and a main surface on a side opposite to the main surface; a semiconductor device mounted on the main surface; and a heat sink attached to the main surface via an insulation sheet having a thermal conductivity, wherein the substrate includes a through hole passing from the main surface to the main surface, the semiconductor device includes a plurality of electrodes exposed from a surface facing the main surface and a protrusion formed between the plurality of electrodes to be inserted through the through hole, and the insulation sheet is formed so that a length in a thickness direction of the substrate is larger than a length of a tip end portion of the protrusion protruding from the through hole.

A pin fin placement assembly utilized to form pin fins in a thermal dissipating feature is provided. The pin fin placement assembly may place the pin fins on an IC die disposed in the IC package. The pin fin placement assembly may assist massively placing the pin fins with desired profiles and numbers on desired locations of the IC die. The plurality of pin fins is formed in a first plurality of apertures in the pin fin placement assembly. A thermal process is then performed to solder the plurality of pin fins on the IC die.

A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

A method includes forming a package component, including forming a thermal via extending through a substrate; and bonding a die to the thermal via; attaching the thermal via of the package component to a first conductive pad of a package substrate, wherein the package substrate includes a heat pipe underneath the first conductive pad; and attaching a support structure to a second conductive pad of the package substrate, wherein the heat pipe is underneath the second conductive pad, wherein the support structure includes a first thermoelectric cooler.

A power semiconductor package includes: a metal plate having opposing first and second sides; a lateral wall extending along a rim of the first side of the metal plate and surrounding an inner portion of the first side; at least one die carrier arranged over the inner portion of the first side of the metal plate; a power semiconductor die arranged over and electrically coupled to the die carrier, the die carrier electrically isolating the power semiconductor die from the metal plate; and a printed circuit board (PCB) arranged over the lateral wall and covering the inner portion of the first side of the metal plate such that the die carrier and the power semiconductor die are arranged within an interior volume of the power semiconductor package encapsulated by the inner portion of the first side of the metal plate, the lateral wall and the PCB.

Provided is a semiconductor package including: a substrate including a first surface a and second surface opposite to the first surface, the substrate further including a first cavity extending from the first surface to the second surface; first and second lower semiconductor chips, wherein the first and second lower semiconductor chips are vertically stacked in the first cavity; a first redistribution substrate on the first surface of the substrate; a first upper semiconductor chip on the first redistribution substrate; a second upper semiconductor chip on the first redistribution substrate and horizontally spaced apart from the first upper semiconductor chip; and a first bridge chip in the first redistribution substrate that connects the first and second upper semiconductor chips, wherein the first lower semiconductor chip is spaced apart from the first redistribution substrate, and wherein the second lower semiconductor chip is directly connected to the first redistribution substrate.

An electronic device is provided. The electronic device includes an electronic unit and a circuit structure. The circuit structure is electrically connected to the electronic unit. The circuit structure includes a first conductive layer, a first insulating layer and a first heat dissipation element. The first insulating layer is disposed between the first conductive layer and the electronic unit. The first heat dissipation element is in contact with the first conductive layer. Moreover, a heat transfer coefficient of the first dissipation element is greater than a heat transfer coefficient of the first insulating layer and less than a heat transfer coefficient of the first conductive layer.

A semiconductor package includes a redistribution structure including a redistribution insulating layer and a redistribution pattern, a first semiconductor device mounted on the redistribution structure, vertical connection conductors on the redistribution structure and apart from the first semiconductor device in a horizontal direction, a second semiconductor device mounted on the vertical connection conductors, and a heat-dissipation plate mounted on the first semiconductor device, wherein the heat-dissipation plate includes a main body and a plurality of protrusions protruding from the main body in the horizontal direction.

In an embodiment, a device includes: a die stack over and electrically connected to an interposer, the die stack including a topmost integrated circuit die including: a substrate having a front side and a back side opposite the front side, the front side of the substrate including an active surface; a dummy through substrate via (TSV) extending from the back side of the substrate at least partially into the substrate, the dummy TSV electrically isolated from the active surface; a thermal interface material over the topmost integrated circuit die; and a dummy connector in the thermal interface material, the thermal interface material surrounding the dummy connector, the dummy connector electrically isolated from the active surface of the topmost integrated circuit die.