A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.

A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a metal-to-metal bond and a heat dissipation feature over the first die. The heat dissipation feature includes a thermal base over the first die and surrounding the second die, wherein the thermal base is made of a metal; and a plurality of thermal vias on the thermal base; and an encapsulant over first die and surrounding the second die, surrounding the thermal base, and surrounding the plurality of thermal vias.

A temperature regulation unit (10) includes a plurality of stacked porous metal structures (for example, metal fiber structures (40, 42)) each of which has a plurality of rod-shaped members (32, 34) extending parallel to each other so as to be spaced apart from each other and a connection member (24, 26) connecting the respective rod-shaped members (32, 34) and is formed from metal, the respective rod-shaped members (32, 34) of the respective porous metal structures extend parallel to each other, and a flow passage (50) for a fluid is formed in a gap between the respective rod-shaped members (32, 34).

A semiconductor device package includes an interconnect structure with a first surface having at least one die thereon and a second surface that is opposite the first surface and is configured to be coupled to an external device. A protective structure on the first surface of the interconnect structure exposes a heat dissipating surface facing away from the interconnect structure in one or more directions. Related devices and fabrication methods are also discussed.

Methods, systems, and devices for thermal structures for hybrid bonding are described. Thermal structures may be formed within stacked memory devices, such as memory dies, to increase heat dissipation and thermal conductivity in a system. For example, a device may include one or more active contacts coupled with through-silicon vias (TSVs) extending through a silicon substrate, which may transport signaling or power. The device may also include one or more inactive contacts that may not be directly coupled with one or more TSVs. To increase heat dissipation, one or more vias may be formed between non-active contacts and a metal layer. In some examples, vias may be formed for conductors that are at least partially above a respective metal layer conductor. In some cases, a system may include stacks of bonded pairs of devices, or stacks of bonded trios of devices.

Methods of fabricating a 3D semiconductor device including: forming a first level including a first single crystal layer and first transistors, includes a single crystal channel; forming a first metal layer in the first level and a second metal layer overlaying the first metal layer; forming memory control circuits in the first level; forming a second level including second transistors, where at least one of the second transistors includes a metal gate; forming a third level including third transistors; forming a fourth level including fourth transistors, where the second level includes first memory cells, where the fourth level includes second memory cells, where the memory control circuits include control of data written into the first memory cells and into the second memory cells, where at least one of the transistors includes a hafnium oxide gate dielectric.

A package and method is disclosed. In one example, the package comprises a component assembly section, at least one electronic component being assembled with the component assembly section, at least one lead section being electrically coupled with the at least one electronic component and/or with the component assembly section, an encapsulant at least partially encapsulating the at least one electronic component and partially encapsulating the component assembly section and the at least one lead section so that part of the component assembly section and part of the at least one lead section are exposed beyond the encapsulant. A thermoplastic structure covers an exposed area of the component assembly section without covering an exposed area of the at least one lead section.

A cooling structure includes a flow path-forming member that forms a flow path for a refrigerant to pass through, wherein: the flow path-forming member includes, on a basal inner wall thereof, a cooling fin installation section provided with at least one cooling fin projecting from the basal inner wall toward an inner side of the flow path, the cooling fin installation section being disposed separately from side inner walls of the flow path-forming member; and the flow path-forming member includes, on a side inner wall thereof, at least one obstacle projecting from the side inner wall toward the inner side of the flow path.

In a temperature regulation unit (10), a flow passage (50) for a fluid is formed between a plurality of rod-shaped members (30) which extend parallel to each other so as to be spaced apart from each other and are formed from porous metal; in the flow passage (50), the fluid flows along a flow direction which is a direction orthogonal to a direction in which the rod-shaped members (30) extend; and the flow passage (50) meanders along the flow direction.

A semiconductor package includes a leadframe comprising first leads and second leads, a substrate connected between the first leads and the second leads, a base plate, a first semiconductor transistor die connected between the base plate and the substrate and including a first source pad, a first drain pad, and a first gate pad, a second semiconductor transistor die connected between the base plate and the substrate and comprising a second source pad, a second drain pad, and a second gate pad, wherein the first semiconductor die and the second semiconductor die are interconnected to form a half-bridge circuit, wherein the first source pad of the first semiconductor die is electrically connected with the second drain pad of the second semiconductor die, an encapsulant embedding the first semiconductor die, the second semiconductor transistor die, and horizontal portions of the first leads and the second leads.