A semiconductor wafer transport apparatus includes a frame, a transport arm movably mounted to the frame and having at least one end effector movably mounted to the arm so the at least one end effector traverses, with the arm as a unit, in a first direction relative to the frame, and traverses linearly, relative to the transport arm, in a second direction, and an edge detection sensor mounted to the transport arm so the edge detection sensor moves with the transport arm as a unit relative to the frame, the edge detection sensor being a common sensor effecting edge detection of each wafer simultaneously supported by the end effector, wherein the edge detection sensor is configured so the edge detection of each wafer is effected by and coincident with the traverse in the second direction of each end effector on the transport arm.

A method of making an interconnect substrate, comprising disposing an embedded component and at least one tracking identifier in a substrate core, and planarizing the substrate core to form a planar surface, forming a conductive layer over a frontside planar surface, disposing a layer of dielectric over the frontside planar surface, the embedded component, and the conductive layer, rotating the substrate core such that a back surface of the substrate core is configured for processing, and forming a conductive layer over the back surface of the substrate core.

The present disclosure provides a method for manufacturing a semiconductor device having a mark. The method includes: providing a substrate including a device region and a peripheral region adjacent to the device region; forming an interconnect layer over the substrate; depositing a first dielectric layer on the interconnect layer; forming a redistribution layer (RDL) over the first dielectric layer in the device region; depositing a second dielectric layer on the RDL in the device region and the first dielectric layer in the device region and the peripheral region; and removing portions of the second dielectric layer, the first dielectric layer and the interconnect structure in the peripheral region to form the mark in the peripheral region.

A semiconductor package includes a first semiconductor chip, a sealing layer molding the first semiconductor chip, and an upper connection structure on the sealing layer, wherein the upper connection structure includes an insulating layer. The insulating layer includes marking patterns defined by a first region and a second region, the first region being at at least a portion of the insulating layer and having a first light transmittance value, the second region being at at least a portion of the first region and having a second light transmittance value different from the first light transmittance value.

Methods, systems, and devices for identification marking cavity filling for semiconductor packages are described. A semiconductor device may be formed to be relatively less susceptible to surface failures, including failure initiated by stress risers associated with identification markings. For example, a mold compound material may be formed over one or more semiconductor dies of the semiconductor device. One or more identification markings may be formed in the mold compound material based on forming one or more cavities into a surface of the material. A second material may be formed in the one or more cavities and may fill each of the cavities. The second material may be a crack-resistant material. The second material may be formed through one or more apertures of a stencil, or the second material may be formed by applying the second material over an entirety of the surface of the semiconductor device.

The invention concerns a method of manufacturing an assembly of electronic components (3) on the front surface of a semiconductor wafer (1) comprising a plurality of field areas (4), each area (4) comprising at least one field (2) and each field (2) comprising at least one electronic component (3). The method comprises a plurality of photolithography steps to form a stack of layers forming each electronic component (3), each photolithography step comprises the application of a mask successively on each field (2) in photolithography equipment. One of the masks further comprises an identification pattern, said mask being called identification mask. At the photolithography step associated with the identification mask, as least one photolithographic parameter of the photolithography equipment is different for each field area (4), to expose the identification pattern differently in each field area (4).

A glass substrate for semiconductors includes a first principal surface and a second principal surface disposed to face opposite the first principal surface, in which a wiring layer is to be formed on at least one of the first principal surface and the second principal surface. The glass substrate for semiconductors has a hole formed in at least one of the first principal surface and the second principal surface, and the glass substrate for semiconductors has an identification mark for identifying the glass substrate between the first principal surface and second principal surface. The minimum value of a shortest distance and a shortest distance is equal to or greater than 100 m. A ratio (d1 ave/d2 ave) is 0.03-33. A ratio (d3 ave/d ave) is 0.01-0.50.

A semiconductor package component which has an outer profile including an oblique package edge obliquely interconnecting between two adjacent side walls. The semiconductor package component includes a first redistribution layer (RDL) unit, a chip unit, a dummy die unit, an encapsulation layer, and a second RDL unit. The chip unit is disposed on the first RDL unit. The dummy die unit includes a dummy die that is disposed on the first RDL unit, and has a dummy die edge which extends in a direction parallel to the oblique package edge. A method for making the semiconductor package component is also disclosed.

According to the present disclosure, a semiconductor apparatus comprises a housing a semiconductor chip installed in the housing, and a first radio tag installed on the housing. The first radio tag is installed in a state where rewriting from outside is not limited.

A semiconductor package including a lower substrate, a lower semiconductor chip mounted on the lower substrate, a lower mold layer on the lower substrate and enclosing the lower semiconductor chip, a redistribution layer on the lower mold layer, and a vertical connection terminal around the lower semiconductor chip and connecting the lower substrate to the redistribution layer may be provided. The lower semiconductor chip may include a cognition mark at a top surface thereof. The cognition mark may include a marking pattern having an intaglio shape at the top surface of the lower semiconductor chip, and a molding pattern filling an inner space of the marking pattern. A first material constituting the molding pattern may be the same as a second material constituting the lower mold layer.