The present disclosure relates to the field of semiconductor packaging technologies, and in particular, to a panel-level chip packaging structure and method based on a steel plate platform. The packaging structure includes: a steel plate; a gold-nickel layer plated on the steel plate, where the gold-nickel layer is provided with upwardly protruding pins corresponding to a chip; the chip flipped to the corresponding pins; and a molded body coating the corresponding chip and the gold-nickel layer. According to the packaging structure and method of the present disclosure, an overall thickness of a chip-packaged product can be reduced. A wire bonding process and an electroplating process are further omitted, so that the overall thickness of chip packaging can be further reduced. An ultra-thin packaging structure can be implemented, the chip packaging efficiency can further be improved, and a complete-process chip packaging cycle can be shortened.

An object is to provide a technique that improves the moisture uptake resistance of a semiconductor device. A semiconductor device includes a resin insulating sheet, a heat spreader provided on the resin insulating sheet, a semiconductor element mounted on the heat spreader, a lead frame having one end portion thereof connected to the semiconductor element, a first resin body that seals the resin insulating sheet, the heat spreader, the semiconductor element, and the one end portion of the lead frame with a rear surface of the resin insulating sheet being exposed, and a second resin body that seals the first resin body with the rear surface of the resin insulating sheet being exposed.

An optoelectronic package structure is provided. The optoelectronic package structure includes a carrier and a photonic component. The carrier includes an upper surface and a first lateral surface. The photonic component is disposed over an upper surface of the carrier and includes an optical portion. The carrier includes a recessed portion recessed from the first lateral surface of the carrier, and the optical portion of the photonic component is located within the recessed portion of the carrier from a top view perspective.

An electronic device and a manufacturing method thereof are provided. The electronic device includes a substrate, at least one electronic unit, an adhesive layer, an insulating layer, and a conductive structure. The substrate has at least one recess. The electronic unit is disposed in the recess, and the adhesive layer is disposed between the electronic unit and a bottom surface of the recess. The insulating layer is disposed on the electronic unit and the recess. The conductive structure is disposed on the insulating layer, and the conductive structure penetrates through the insulating layer to be electrically connected to the electronic unit.

A semiconductor structure includes a substrate having a first device region and a second device region in proximity to the first device region. A first trench isolation structure is disposed in the substrate between the first device region and the second device region. The first trench isolation structure includes a first bottom surface within the first device region and a second bottom surface within the second device region. The first bottom surface is lower than the second bottom surface. The first trench isolation structure includes a first top surface within the first device region and a second top surface within the second device region. The first top surface is coplanar with the second top surface.

A power semiconductor device according to the present invention is provided with: a first circuit body constituting an upper arm of an inverter circuit for converting a DC current into an AC current; a second circuit body constituting a lower arm of the inverter circuit; and a circuit board that has therein a through-hole in which the first circuit body and the second circuit body are disposed and that has an intermediate board between the first circuit body and the second circuit body. The intermediate board has an AC wiring pattern for transmitting the AC current, and the first circuit body and the second circuit body are connected to the AC wiring pattern so as to be in surface contact with the AC wiring pattern.

A die includes a substrate, a conductive pad, a connector a protection layer, and a passivation layer. The conductive pad is disposed over the substrate. The connector is disposed on the conductive pad. The connector comprises a seed layer and a conductive post on the seed layer. The protection layer laterally covers the connector. The passivation layer is disposed between the protection layer and the conductive pad. The conductive post is separated from the passivation layer and the protection layer by the seed layer.

Proposed is a semiconductor package having air via, which can reduce RF loss and increase the frequency bandwidth by reducing dielectric loss and parasitic capacitance components of semiconductor packages by providing an air via vertically in the space between first, second, and third dielectric layers, which are sequentially stacked with a signal line pad and a ground pad, thereby improving package performance.

This application is directed to packaging technology for providing an electronic device (e.g., a memory device). A memory device includes a stack of memory chips, a device substrate, and a conductive wire. The stack of memory chips includes a first memory chip having a chip pad that is formed on a surface of the first memory chip. The device substrate includes a plurality of substrate pads formed on a front surface of the device substrate. The front surface has a front opening, and the device substrate receives the stack of memory chips via the front opening of the front surface. The conductive wire is coupled to the front surface and the stack of memory chips, and is configure to couple the chip pad and one of the substrate pads electrically. In some embodiments, the device substrate includes a cutout opening that goes through an entire thickness of the device substrate.

A semiconductor package including a package substrate defining a cavity therein; a first semiconductor chip on the package substrate; a first bump between the package substrate and the first semiconductor chip, the first bump electrically connecting the package substrate and the first semiconductor chip; a second semiconductor chip on the package substrate, the second semiconductor chip being at least partially in the cavity; a first bonding wire electrically connecting the package substrate and the second semiconductor chip; and an underfill layer covering the first bump and at least a portion of the first bonding wire.