A package comprising a first substrate; an integrated device coupled to the first substrate, wherein the integrated device comprises a plurality of back side metallization interconnects; and a second substrate coupled to the first substrate through a first plurality of solder interconnects, wherein the second substrate is coupled to the plurality of back side metallization interconnects through the second plurality of solder interconnects.

Stacked semiconductor packages with features to mitigate trace exposer and associated systems and methods are disclosed herein. In some embodiments, the stacked semiconductor package includes a base substrate, a stack of dies carried by the base substrate, and a mold material deposited at least partially encapsulating the stack of dies. The base substrate can include an active surface and a back surface opposite the active surface. Further, the active surface can include one or more cuts into a peripheral portion of the active surface (e.g., stepped structures at the peripheral edges of the base substrate). The base substrate can also include a plurality of bond pads carried by the active surface over the peripheral portion. Still further, the mold material can fill each of the one or more cuts in the active surface, thereby insulating the bond pads from exposure at a sidewall of the stacked semiconductor package.

A semiconductor device includes: a conductive portion; and a semiconductor element mounted on the conductive portion, wherein the conductive portion is made of a plating layer, wherein the conductive portion includes a mounting portion having a mounting surface on which the semiconductor element is mounted, and a terminal portion extending to an opposite side of the semiconductor element with respect to the mounting portion, wherein the mounting portion extends in a first direction along the mounting surface more than the terminal portion, and wherein the mounting portion and the terminal portion are integrally formed.

The present invention relates to a ceramic substrate and a method for manufacturing the same, the ceramic substrate comprising: a ceramic base material; a first electrode pattern and a second electrode pattern formed on the upper and lower surfaces of the ceramic base material; and a third electrode pattern which is formed on the upper surface of the ceramic base material and is spaced apart from the first electrode pattern, wherein a volume ratio obtained by dividing the total volume of the first electrode pattern by the total volume of the second electrode pattern may be 0.9 to 1.1.

A semiconductor module may include a package substrate including a first surface and an opposite second surface, a semiconductor chip on the first surface of the package substrate, a plurality of pads on the second surface of the package substrate, and a plurality of solder balls connected to the plurality of pads, respectively, where the package substrate may include a slit in or on the second surface, at least a portion of the slit is disposed between the plurality of solder balls, the slit is spaced apart from the plurality of pads, and a filling layer is in the slit.

An electronic device includes a substrate, a through hole, a first electronic unit, a second electronic unit, a circuit structure, and a third electronic unit. The substrate has a first surface, a second surface opposite the first surface, a first cavity, and a second cavity. A sidewall of the first cavity is connected to the first surface, and a sidewall of the second cavity is connected to the first surface. The through hole extends through the substrate, and a sidewall of the through hole is connected to the first surface and the second surface. The first electronic unit is disposed in the first cavity. The second electronic unit is disposed in the second cavity. The circuit structure is disposed on the first electronic unit and the second electronic unit. The bottom surfaces of the first and second cavities have a roughness ranging from 0 to 2 micrometers.

A component carrier includes a stack with at least one electrically conductive layer structure, at least one electrically insulating layer structure, a cavity delimited at a bottom side at least partially by a top side of a stepped metal structure of the at least one electrically conductive layer structure, and a component embedded in the cavity and arranged on the stepped metal structure. A bottom side of the stepped metal structure has a flat surface extending continuously along at least one horizontal direction. Further, a top side of the stepped metal structure comprises a recess in and/or around a surface portion on which the component is arranged.

The present disclosure as an embodiment is to provide a wiring structure including a first wiring pattern; an insulation layer covering at least a portion of the first wiring pattern; a second wiring pattern disposed on the insulation layer; a via penetrating at least a portion of the insulation layer and electrically connecting the first wiring pattern and the second wiring pattern; and a protruding pattern extending into the insulation layer and having at least a portion thereof embedded in the insulation layer, the protruding pattern disposed on the first wiring pattern and connected thereto, and positioned spaced apart from the via and surrounding at least a portion of the via on the first wiring pattern.

There is provided a semiconductor device 1, comprising: a housing comprising a housing electrode 4; and at least one semiconductor chip 20 arranged within the housing; wherein the housing electrode 4 comprises a deformable portion 15, and the deformable portion 15 is configured to deform when a pressure difference between an interior and an exterior of the housing exceeds a threshold differential pressure or a temperature at the deformable portion exceeds a threshold temperature, so as to transform the housing from a hermetically sealed housing to an open housing in fluid communication with the exterior.

A package structure is provided. The package structure includes a package substrate, an inorganic substrate over the package substrate, and a package component over the inorganic substrate. The package structure includes a plurality of conductive connectors penetrating the inorganic substrate and electrically connected to the package component and the package substrate. The package structure also includes an underfill formed around the conductive connectors and between the package component and the inorganic substrate.