A semiconductor package including a lower substrate, a lower semiconductor chip mounted on the lower substrate, a lower mold layer on the lower substrate and enclosing the lower semiconductor chip, a redistribution layer on the lower mold layer, and a vertical connection terminal around the lower semiconductor chip and connecting the lower substrate to the redistribution layer may be provided. The lower semiconductor chip may include a cognition mark at a top surface thereof. The cognition mark may include a marking pattern having an intaglio shape at the top surface of the lower semiconductor chip, and a molding pattern filling an inner space of the marking pattern. A first material constituting the molding pattern may be the same as a second material constituting the lower mold layer.

A semiconductor package includes a support wiring structure, a semiconductor chip on the support wiring structure, a connection structure on the support wiring structure and spaced apart from the semiconductor chip in a horizontal direction, an interposer including a central portion and an outer portion and having a recess portion provided on a lower surface of the central portion facing the semiconductor chip, wherein the central portion is on the semiconductor chip and the connection structure is connected to the outer portion, and a metal plate disposed along a portion of a surface of the recess portion inside the interposer, wherein the metal plate extends along a side surface of the outer portion of the interposer and the lower surface of the central portion of the interposer, and the metal plate has a cavity passing through a vicinity of a center of the metal plate planarly.

A structure includes a substrate having a frontside and a backside. A first electrode is in a first insulator layer and is adjacent to the frontside of the substrate. The first electrode is part of a redistribution layer (RDL). A second electrode is between the substrate and the first electrode. A dielectric-filled trench in the substrate is under the first electrode and the second electrode, the dielectric-filled trench may extend fully to the backside of the substrate. The structure provides a galvanic isolation that exhibits less parasitic capacitance to the substrate from the lower electrode.

Methods of manufacturing a sealed electrical device for embedded integrated circuit (IC) chips are described, as well as the resulting devices themselves. The sealed electrical device is created by removing material from a substrate to form a pocket in the substrate. An unencapsulated, or bare, IC chip can be placed within the pocket with connection pads of the IC chip facing outward. A gap between the IC chip and a side of the pocket can be filled with a filler. An uncured polymer can be cast over the substrate, which can be allowed to cure into a flat polymer sheet. Conductive traces can be patterned on the polymer sheet and to the connection pads of the IC chip. The conductive traces can then be coated with polymer to form a ribbon cable. Substrate can then be removed from underneath the ribbon cable, leaving substrate around the pocket to protect the IC chip.

Methods of manufacturing a sealed electrical device for embedded integrated circuit (IC) chips are described, as well as the resulting devices themselves. The sealed electrical device is created by removing material from a substrate to form a pocket in the substrate. An unencapsulated, or bare, IC chip can be placed within the pocket with connection pads of the IC chip facing outward. A gap between the IC chip and a side of the pocket can be filled with a filler. An uncured polymer can be cast over the substrate, which can be allowed to cure into a flat polymer sheet. Conductive traces can be patterned on the polymer sheet and to the connection pads of the IC chip. The conductive traces can then be coated with polymer to form a ribbon cable. Substrate can then be removed from underneath the ribbon cable, leaving substrate around the pocket to protect the IC chip.

The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor device package. In certain embodiments, a glass or silicon substrate is patterned by laser ablation to form structures for subsequent formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor device package, which may have one or more embedded double-sided dies therein. In certain embodiments, an insulating layer is formed over the substrate by laminating a pre-structured insulating film thereon. The insulating film may be pre-structured by laser ablation to form structures therein, followed by selective curing of sidewalls of the formed structures.

A power module includes a insulation substrate, a first and a second input terminal supported by the insulation substrate, a plurality of arm circuits provided on the insulation substrate, and a plurality of output terminals corresponding to the plurality of arm circuits. The arm circuits each include a part of a wiring pattern formed on the insulation substrate, and a first switching element and a second switching element mutually connected in series via the part of the wiring pattern. The output terminals are each connected to a connection point between the first switching element and the second switching element in a corresponding one of the plurality of arm circuits. The plurality of arm circuits are located so as to overlap with a circle surrounding the first input terminal, as viewed in a thickness direction the insulation substrate.

Passive devices may be embedded into a cavity in a package substrate, with electrical contacts of the passive device on a contact surface orthogonal to a surface of the package substrate and extending through the package substrate. The electrical contacts of the passive device may be coupled to vias coupled to a power supply to provide capacitive decoupling. One or more through-hole vias (THVs), which provide current to ICs on the package substrate, may be excluded from the package substrate to accommodate the passive device. Embedding the passive devices in the cavity of the package substrate with the contact surface orthogonal to, rather than parallel to, the surface of the package substrate, reduces an area occupied by the passive device. In this manner, a number of the THVs excluded from the package substrate is reduced, which results in a smaller impact to the resistance of the power supply network.

A micro light-emitting diode display unit including a driving chip, at least one pixel, and a conductor is disclosed. The pixel includes multiple micro light-emitting diodes (micro-LEDs) disposed on a top of the driving chip. Orthogonal projections of the micro-LEDs are all covered by an orthogonal projection of the driving chip. The conductor is disposed at an outer side of the driving chip, and extends from a side adjacent to a top portion of the driving chip on which the micro-LEDs are disposed to a side away from the micro-LEDs, and is connected to an outside circuit. A manufacturing method of a micro light-emitting diode display unit is also disclosed.

A sensor package includes a circuit substrate, a sensor die, an electrical connection, a dielectric dam, a cover layer, and an encapsulant. The circuit substrate includes a first side, a second side opposite to the first side, and a cavity recessed from the first side toward the second side. The sensor die is disposed in the cavity and includes a first side, a sensing area on the first side, and a second side opposite to the first side and facing the circuit substrate. The electrical connection electrically connects the first sides of the sensor die and the circuit substrate. The dielectric dam is disposed on the first side of the circuit substrate and outside the cavity, and the dielectric dam partially covers the electrical connection. The encapsulant is disposed on the first side of the circuit substrate and laterally covers the dielectric dam and the cover layer.