A semiconductor device includes a substrate. The substrate has a first surface and a side surface. The semiconductor device has a plurality of electrodes on the first surface. The semiconductor device has a side surface cover that covers the side surface. The semiconductor device has a front surface cover. The first surface has an electrode-free portion covered with the front surface cover. The plurality of electrodes includes one or more electrode pairs, at least one of the one or more electrode pairs being disposed along an edge of the first surface. The side surface cover is connected to a portion between at least one electrode pair out of the front surface cover. A comparative tracking index of a material for forming the front surface cover and the side surface cover is greater than a comparative tracking index of a material for forming the substrate.

A semiconductor device includes a circuit substrate, a first semiconductor element, a second semiconductor element, and a connection element. The circuit substrate includes a first pad. The first semiconductor element is disposed on the circuit substrate and includes a second pad and a third pad. The second semiconductor element is disposed on the circuit substrate. The connection element is disposed on the circuit substrate and electrically connects the first semiconductor element and the second semiconductor element. The connection element includes a fourth pad. The second pad is bonded to the first pad through a conductive material, and the third pad is directly bonded to the fourth pad.

An optical module includes a wiring substrate, electronic components mounted on the wiring substrate, and a waveguide component mounted on the wiring substrate and connecting the electronic components to each other. The waveguide component includes a waveguide substrate including an optical waveguide, a first surface, and a second surface opposite the first surface. A photonic integrated circuit element is mounted on the first surface of the waveguide substrate and optically connected to the optical waveguide. An electrical integrated circuit element is mounted on the second surface of the waveguide substrate and electrically connected to the photonic integrated circuit element.

A semiconductor module includes: a board that includes a wiring portion formed on at least one surface and a hole portion having an opening on the at least one surface side; and a body portion that is disposed on one surface side of the board and is sealed by a resin, and a lead portion having a plate shape that extends toward an outside from a side surface of the body portion. In at least one semiconductor package, a part of the body portion is inserted into the hole portion, and the lead portion extends along a surface of the board, and a lower surface of the lead portion is bonded to the wiring portion.

A backside conductors is configured such that an electrode for electrical connection to an outside is formed in addition to a heat sink in correspondence with each of a plurality of cavity structures, and a support member is formed so as to be at a position separated from dicing lines for dividing each of the cavity structures into an individual piece, arranged closer to the dicing lines than to the heat sink and the electrode, and interposed between a molding die and a board at a time of integral molding with the mold material.

A backside conductors is configured such that an electrode for electrical connection to an outside is formed in addition to a heat sink in correspondence with each of a plurality of cavity structures, and a support member is formed so as to be at a position separated from dicing lines for dividing each of the cavity structures into an individual piece, arranged closer to the dicing lines than to the heat sink and the electrode, and interposed between a molding die and a board at a time of integral molding with the mold material.

Provided is a semiconductor element including: a multilayer structure including: a conductive substrate; and an oxide semiconductor film arranged directly on the conductive substrate or over the conductive substrate via a different layer, the oxide semiconductor film including an oxide, as a major component, containing gallium, the conductive substrate having a larger area than the oxide semiconductor film.

Microelectronic assemblies with glass cores with tapered insulator edges, as well as related devices and fabrication techniques, are disclosed. In one aspect, a microelectronic assembly according to an embodiment of the present disclosure may include a glass core (e.g., a layer of glass or a glass structure) having a first face, and an insulator material having a bottom face, a top face opposite the bottom face, and an outer edge extending between the bottom face and the top face. The top bottom face of the insulator material is on the glass core, and the outer edge of the insulator material tapers from a first perimeter at the bottom face to a second perimeter at the top face. The taper of the outer edge results in the first perimeter being larger than the second perimeter.

A 3D integrated circuit package is provided. The 3D integrated circuit package includes a substrate structure, a first interposer, a second interposer, a first semiconductor die, and a second semiconductor die. The substrate structure has a first surface and a second surface opposite to the first surface. The first interposer is disposed over the first surface of the substrate structure. The second interposer is disposed over the first interposer. The first and the second semiconductor dies are disposed over the first surface of the substrate structure, and the first and the second semiconductor dies are bonded to two opposite sides of the second interposer, respectively. The substrate structure includes a thermal enhancement portion, and at least one of a thermal conductivity or a geometry of the thermal enhancement portion is different from that of other portions of the substrate structure.

A semiconductor package includes a package substrate; a semiconductor die vertically stacked on the package substrate; a redistribution layer (RDL) including a dielectric material and metal features that electrically connect the semiconductor die to the package substrate, the RDL having a first Young's modulus; a first underfill layer disposed between the RDL and the semiconductor die; and stress buffers embedded in the RDL below corners of the semiconductor die, each stress buffer having a second Youngs modulus that is at least 30% less than the first Youngs modulus.