A semiconductor package includes a leadframe having a die pad and a plurality of pins disposed around the die pad, a metal interposer attached to a top surface of the die pad, and a semiconductor die attached to a top surface of the metal interposer. A plurality of bond wires with same function is bonded to the metal interposer. The die pad, the metal interposer and the semiconductor die are stacked in layers so as to form a pyramidal stack structure.

There is provided a package substrate that improves a yield and reliability of a semiconductor package. The package substrate includes a unit area including a plurality of semiconductor chip mounting areas and a scribe lane disposed between adjacent ones of the semiconductor chip mounting areas, an edge area surrounding the unit area, and a trench formed in the edge area, the trench configured to receive a mold material for molding a semiconductor chip to be mounted on the semiconductor chip mounting area.

The present invention is an IC module including: a substrate having a through hole; a contact terminal provided on a first surface of the substrate; an IC chip provided on a second surface of the substrate; a holding portion fixed to the substrate and projecting from the substrate; and a fingerprint sensor fixed to the holding portion, wherein the contact terminal is electrically connected to the IC chip via the through hole, and the fingerprint sensor is electrically connected to the IC chip via the holding portion.

In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.

In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.

Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a first layer having a first dielectric, a third dielectric, and a first glass portion between the first dielectric and the third dielectric; a second layer having a second dielectric, a fourth dielectric, and a second glass portion between the second dielectric and the fourth dielectric; and a third layer between the first layer and the second layer, the third layer having a bulk glass material, and wherein the first layer physically couples to a first surface of the third layer and the second layer physically couples to a second surface of the third layer.

Disclosed herein are microelectronic assemblies and related devices and methods for alleviating crack formation and propagation in glass by providing various edge features during or after singulation of a glass panel into individual glass units. In some embodiments, a microelectronic assembly includes a glass core (e.g., a layer of glass including a rectangular prism volume) having a first face, a second face opposite the first face, and an edge between an end of the first face and an end of the second face, and further includes a protection coating on the edge, where a material of the protection coating includes a low-density polystyrene foam, an ionogel, a fiber reinforced resin, a pre-impregnated dielectric, a pre-impregnated fabric, a carbon nanotube reinforced epoxy resin, a metal oxide, a mold material, or a solder resist.

Power semiconductor device assemblies are provided. In one example, a power semiconductor device assembly includes a semiconductor device package with one or more terminals. The semiconductor device package comprises one or more wide bandgap semiconductor die. The power semiconductor device assembly includes a support structure. The semiconductor device package is mounted onto the support structure. The power semiconductor device assembly includes an underfill structure. The underfill structure is at least partially on the support structure and the semiconductor device package.

A semiconductor package may include a package substrate, an interposer on the package substrate, photonics modules in the interposer and configured to perform communication based on optical signals, and a semiconductor chip on the interposer. A core substrate of the interposer may include through electrodes and cavities, where the through electrodes may extend from an upper surface of the core substrate to a lower surface of the core substrate. The cavities may extend from the upper surface of the core substrate to an inner portion of the core substrate where the through electrodes are not disposed. One of the photonics modules may be in each of the cavities. Each photonics module may include a photonics integrated circuit chip, and an electronic integrated circuit chip and an optical transmissive layer on an upper surface of the photonics integrated circuit chip.

The present disclosure relates to a semiconductor package, and the semiconductor package according to an embodiment includes a substrate having a recess at an edge; a waveguide structure in the recess, the waveguide structure comprising an internal interconnector configured to be connected to an external interconnector; an optical integrated circuit above the waveguide structure, the optical integrated circuit optically connected to the waveguide structure; an electronic integrated circuit on the optical integrated circuit; a semiconductor chip on the electronic integrated circuit; a first conductive post connecting the substrate and the electronic integrated circuit; and a second conductive post connecting the substrate and the semiconductor chip, wherein a first side surface of the waveguide structure is aligned with a side surface of the substrate.